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[/] [tinycpu/] [trunk/] [testbench/] [memory_tb.vhd] - Diff between revs 7 and 18

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Rev 7 Rev 18
Line 9... Line 9...
 
 
-- Component Declaration for the Unit Under Test (UUT)
-- Component Declaration for the Unit Under Test (UUT)
 
 
  component memory
  component memory
    port(
    port(
      Address: in std_logic_vector(15 downto 0); --memory address
      Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
      Write: in std_logic; --write or read
      WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
      UseTopBits: in std_logic;  --if 1, top 8 bits of data is ignored and not written to memory
      WriteEnable: in std_logic;
      Clock: in std_logic;
      Clock: in std_logic;
      DataIn: in std_logic_vector(15 downto 0);
      DataIn: in std_logic_vector(15 downto 0);
      DataOut: out std_logic_vector(15 downto 0);
      DataOut: out std_logic_vector(15 downto 0)
      Reset: in std_logic
 
    );
    );
  end component;
  end component;
 
 
 
 
  --Inputs
  --Inputs
  signal Address: std_logic_vector(15 downto 0) := (others => '0');
  signal Address: std_logic_vector(15 downto 0) := (others => '0');
  signal Write: std_logic := '0';
  signal WriteWord: std_logic := '0';
  signal UseTopBits: std_logic := '0';
  signal WriteEnable: std_logic := '0';
  signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
  signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
  signal Reset: std_logic := '0';
 
 
 
  --Outputs
  --Outputs
  signal DataOut: std_logic_vector(15 downto 0);
  signal DataOut: std_logic_vector(15 downto 0);
 
 
  signal Clock: std_logic;
  signal Clock: std_logic;
Line 38... Line 36...
BEGIN
BEGIN
 
 
  -- Instantiate the Unit Under Test (UUT)
  -- Instantiate the Unit Under Test (UUT)
  uut: memory PORT MAP (
  uut: memory PORT MAP (
    Address => Address,
    Address => Address,
    Write => Write,
    WriteWord => WriteWord,
    UseTopBits => UseTopBits,
    WriteEnable => WriteEnable,
    Clock => Clock,
    Clock => Clock,
    DataIn => DataIn,
    DataIn => DataIn,
    DataOut => DataOut,
    DataOut => DataOut
    Reset => Reset
 
  );
  );
 
 
  -- Clock process definitions
  -- Clock process definitions
  clock_process :process
  clock_process :process
  begin
  begin
Line 60... Line 57...
 
 
  -- Stimulus process
  -- Stimulus process
  stim_proc: process
  stim_proc: process
    variable err_cnt: integer :=0;
    variable err_cnt: integer :=0;
  begin
  begin
    -- hold reset state for 100 ns.
    wait for 50 ns;
    Reset <= '1';
 
    wait for 100 ns;
 
 
 
    wait for clock_period*10;
 
 
 
    --case 1
    Address <= x"0000";
    Reset <= '0';
    WriteWord <= '1';
    Write <= '0';
    WriteEnable <='1';
    wait for 10 ns;
    DataIn <= x"1234";
    Address <= "0000000000001000";
 
    DataIn <= "1000000000001000";
 
    Write <= '1';
 
    UseTopBits <= '1';
 
    wait for 10 ns;
    wait for 10 ns;
    Write <= '0';
    WriteWord <= '0';
 
    WriteEnable <= '0';
    wait for 10 ns;
    wait for 10 ns;
    assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
    assert (DataOut = x"1234") report "Basic storage failure" severity error;
 
 
     --case 2
    Address <= x"0022";
    Address <= "0000000000001100";
    WriteWord <= '1';
    DataIn <= "1000000000001100";
    WriteEnable <= '1';
    Write <= '1';
    DataIn <= x"5215";
    UseTopBits <= '1';
    wait for 10 ns;
 
    assert (DataOut = x"1234") report "no-change block ram failure" severity error;
 
    WriteWord <= '0';
 
    WriteEnable <= '0';
 
    Address <= x"0000";
    wait for 10 ns;
    wait for 10 ns;
    Write <= '0';
    assert( DataOut = x"1234") report "Memory retention failure" severity error;
 
    Address <= x"0022";
    wait for 10 ns;
    wait for 10 ns;
    assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
    assert( DataOut = x"5215") report "memory timing is too slow" severity error;
 
 
    -- case 3
    Address <= x"0010";
    Address <= "0000000000001000";
    WriteWord <= '1';
 
    WriteEnable <= '1';
 
    DataIn <= x"1234";
    wait for 10 ns;
    wait for 10 ns;
    assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
    WriteWord <= '0';
 
    WriteEnable <= '0';
    --case 4
    Address <= x"0011";
    Address <= x"0000";
 
    Write <= '1';
 
    DataIn <= x"FFCC";
 
    wait for 10 ns;
    wait for 10 ns;
    UseTopBits <= '0';
    assert (DataOut = x"0012") report "unaligned 8-bit memory read is wrong" severity error;
    DataIn <= x"F0C0";
    WriteWord <='0';
 
    WriteEnable <= '1';
 
    DataIn <= x"0056";
    wait for 10 ns;
    wait for 10 ns;
    UseTopBits <='1';
    WriteEnable <= '0';
    Write <= '0';
 
    wait for 10 ns;
    wait for 10 ns;
    assert (DataOut=x"FFC0") report "ignore top bits error case 4" severity error;
    assert (DataOut = x"0056") report "unaligned 8 bit memory write and then read is wrong" severity error;
 
    Address <= x"0010";
    --case 5
 
    --Address <= x"FFFF";
 
    --Write <= '0';
 
    --wait for 10 ns;
 
    --assert (DataOut=x"FFC0") report "memory out of range error case 5" severity error;
 
 
 
    --case 6 (fetch and store practical)
 
    Address <= x"0012";
 
    wait for 10 ns;
    wait for 10 ns;
    Address <= x"0000";
    assert (DataOut = x"5634") report "aligned memory read after unaligned write is wrong" severity error;
    wait for 5 ns;
    WriteEnable <= '1';
    assert(DataOut=x"FFC0") report "practical fail 1" severity error;
    DataIn <= x"0078";
    Address <= x"00FF";
 
    Write <= '1';
 
    DataIn <= x"1234";
 
    wait for 5 ns;
 
    Write <= '0';
 
    wait for 10 ns;
    wait for 10 ns;
    assert(DataOut=x"1234") report "practical fail 2" severity error;
    WriteEnable <= '0';
 
    wait for 10 ns;
 
    assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
 
 
   assert false
   assert false
   report "Testbench of memory completed successfully!"
   report "Testbench of memory completed successfully!"
   severity note;
   severity note;
 
 

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