| Line 9... |
Line 9... |
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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component memory
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component memory
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port(
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port(
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Address: in std_logic_vector(15 downto 0); --memory address
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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Write: in std_logic; --write or read
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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UseTopBits: in std_logic; --if 1, top 8 bits of data is ignored and not written to memory
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WriteEnable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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Reset: in std_logic
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);
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);
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end component;
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end component;
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--Inputs
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--Inputs
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signal Address: std_logic_vector(15 downto 0) := (others => '0');
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signal Address: std_logic_vector(15 downto 0) := (others => '0');
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signal Write: std_logic := '0';
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signal WriteWord: std_logic := '0';
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signal UseTopBits: std_logic := '0';
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signal WriteEnable: std_logic := '0';
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signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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signal Reset: std_logic := '0';
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--Outputs
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--Outputs
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signal DataOut: std_logic_vector(15 downto 0);
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signal DataOut: std_logic_vector(15 downto 0);
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signal Clock: std_logic;
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signal Clock: std_logic;
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Line 36... |
BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: memory PORT MAP (
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uut: memory PORT MAP (
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Address => Address,
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Address => Address,
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Write => Write,
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WriteWord => WriteWord,
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UseTopBits => UseTopBits,
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WriteEnable => WriteEnable,
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Clock => Clock,
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Clock => Clock,
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DataIn => DataIn,
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DataIn => DataIn,
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DataOut => DataOut,
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DataOut => DataOut
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Reset => Reset
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
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Line 57... |
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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variable err_cnt: integer :=0;
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variable err_cnt: integer :=0;
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begin
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begin
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-- hold reset state for 100 ns.
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wait for 50 ns;
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Reset <= '1';
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wait for 100 ns;
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wait for clock_period*10;
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--case 1
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Address <= x"0000";
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Reset <= '0';
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WriteWord <= '1';
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Write <= '0';
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WriteEnable <='1';
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wait for 10 ns;
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DataIn <= x"1234";
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Address <= "0000000000001000";
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DataIn <= "1000000000001000";
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Write <= '1';
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UseTopBits <= '1';
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wait for 10 ns;
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wait for 10 ns;
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Write <= '0';
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WriteWord <= '0';
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WriteEnable <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001000") report "Storage error case 1" severity error;
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assert (DataOut = x"1234") report "Basic storage failure" severity error;
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--case 2
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Address <= x"0022";
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Address <= "0000000000001100";
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WriteWord <= '1';
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DataIn <= "1000000000001100";
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WriteEnable <= '1';
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Write <= '1';
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DataIn <= x"5215";
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UseTopBits <= '1';
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wait for 10 ns;
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assert (DataOut = x"1234") report "no-change block ram failure" severity error;
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WriteWord <= '0';
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WriteEnable <= '0';
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Address <= x"0000";
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wait for 10 ns;
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wait for 10 ns;
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Write <= '0';
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assert( DataOut = x"1234") report "Memory retention failure" severity error;
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Address <= x"0022";
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001100") report "memory selection error case 2" severity error;
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assert( DataOut = x"5215") report "memory timing is too slow" severity error;
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-- case 3
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Address <= x"0010";
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Address <= "0000000000001000";
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WriteWord <= '1';
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WriteEnable <= '1';
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DataIn <= x"1234";
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut="1000000000001000") report "memory retention error case 3" severity error;
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WriteWord <= '0';
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WriteEnable <= '0';
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--case 4
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Address <= x"0011";
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Address <= x"0000";
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Write <= '1';
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DataIn <= x"FFCC";
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wait for 10 ns;
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wait for 10 ns;
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UseTopBits <= '0';
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assert (DataOut = x"0012") report "unaligned 8-bit memory read is wrong" severity error;
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DataIn <= x"F0C0";
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WriteWord <='0';
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WriteEnable <= '1';
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DataIn <= x"0056";
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wait for 10 ns;
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wait for 10 ns;
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UseTopBits <='1';
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WriteEnable <= '0';
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Write <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (DataOut=x"FFC0") report "ignore top bits error case 4" severity error;
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assert (DataOut = x"0056") report "unaligned 8 bit memory write and then read is wrong" severity error;
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Address <= x"0010";
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--case 5
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--Address <= x"FFFF";
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--Write <= '0';
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--wait for 10 ns;
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--assert (DataOut=x"FFC0") report "memory out of range error case 5" severity error;
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--case 6 (fetch and store practical)
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Address <= x"0012";
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wait for 10 ns;
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wait for 10 ns;
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Address <= x"0000";
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assert (DataOut = x"5634") report "aligned memory read after unaligned write is wrong" severity error;
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wait for 5 ns;
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WriteEnable <= '1';
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assert(DataOut=x"FFC0") report "practical fail 1" severity error;
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DataIn <= x"0078";
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Address <= x"00FF";
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Write <= '1';
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DataIn <= x"1234";
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wait for 5 ns;
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Write <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert(DataOut=x"1234") report "practical fail 2" severity error;
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WriteEnable <= '0';
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wait for 10 ns;
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assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
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assert false
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assert false
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report "Testbench of memory completed successfully!"
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report "Testbench of memory completed successfully!"
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severity note;
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severity note;
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