Line 14... |
Line 14... |
Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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Address: in std_logic_vector(15 downto 0); --memory address (in bytes)
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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WriteWord: in std_logic; --if set, will write a full 16-bit word instead of a byte. Address must be aligned to 16-bit address. (bottom bit must be 0)
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WriteEnable: in std_logic;
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WriteEnable: in std_logic;
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Clock: in std_logic;
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Clock: in std_logic;
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DataIn: in std_logic_vector(15 downto 0);
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DataIn: in std_logic_vector(15 downto 0);
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DataOut: out std_logic_vector(15 downto 0)
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DataOut: out std_logic_vector(15 downto 0);
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Port0: inout std_logic_vector(7 downto 0)
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);
|
);
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end component;
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end component;
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|
|
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--Inputs
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--Inputs
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Line 28... |
Line 29... |
signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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signal DataIn: std_logic_vector(15 downto 0) := (others => '0');
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|
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--Outputs
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--Outputs
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signal DataOut: std_logic_vector(15 downto 0);
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signal DataOut: std_logic_vector(15 downto 0);
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|
|
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--inouts
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signal Port0: std_logic_vector(7 downto 0);
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|
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signal Clock: std_logic;
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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|
|
BEGIN
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BEGIN
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|
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Line 40... |
Line 44... |
Address => Address,
|
Address => Address,
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WriteWord => WriteWord,
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WriteWord => WriteWord,
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WriteEnable => WriteEnable,
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WriteEnable => WriteEnable,
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Clock => Clock,
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Clock => Clock,
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DataIn => DataIn,
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DataIn => DataIn,
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DataOut => DataOut
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DataOut => DataOut,
|
|
Port0 => Port0
|
);
|
);
|
|
|
-- Clock process definitions
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-- Clock process definitions
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clock_process :process
|
clock_process :process
|
begin
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begin
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Line 60... |
Line 65... |
variable err_cnt: integer :=0;
|
variable err_cnt: integer :=0;
|
begin
|
begin
|
wait for 50 ns;
|
wait for 50 ns;
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|
|
|
|
Address <= x"0000";
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Address <= x"0100";
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WriteWord <= '1';
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WriteWord <= '1';
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WriteEnable <='1';
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WriteEnable <='1';
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DataIn <= x"1234";
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DataIn <= x"1234";
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wait for 10 ns;
|
wait for 10 ns;
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WriteWord <= '0';
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WriteWord <= '0';
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WriteEnable <= '0';
|
WriteEnable <= '0';
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wait for 10 ns;
|
wait for 10 ns;
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assert (DataOut = x"1234") report "Basic storage failure" severity error;
|
assert (DataOut = x"1234") report "Basic storage failure" severity error;
|
|
|
Address <= x"0022";
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Address <= x"0122";
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WriteWord <= '1';
|
WriteWord <= '1';
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WriteEnable <= '1';
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WriteEnable <= '1';
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DataIn <= x"5215";
|
DataIn <= x"5215";
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wait for 10 ns;
|
wait for 10 ns;
|
assert (DataOut = x"1234") report "no-change block ram failure" severity error;
|
assert (DataOut = x"1234") report "no-change block ram failure" severity error;
|
WriteWord <= '0';
|
WriteWord <= '0';
|
WriteEnable <= '0';
|
WriteEnable <= '0';
|
Address <= x"0000";
|
Address <= x"0100";
|
wait for 10 ns;
|
wait for 10 ns;
|
assert( DataOut = x"1234") report "Memory retention failure" severity error;
|
assert( DataOut = x"1234") report "Memory retention failure" severity error;
|
Address <= x"0022";
|
Address <= x"0122";
|
wait for 10 ns;
|
wait for 10 ns;
|
assert( DataOut = x"5215") report "memory timing is too slow" severity error;
|
assert( DataOut = x"5215") report "memory timing is too slow" severity error;
|
|
|
Address <= x"0010";
|
Address <= x"0110";
|
WriteWord <= '1';
|
WriteWord <= '1';
|
WriteEnable <= '1';
|
WriteEnable <= '1';
|
DataIn <= x"1234";
|
DataIn <= x"1234";
|
wait for 10 ns;
|
wait for 10 ns;
|
WriteWord <= '0';
|
WriteWord <= '0';
|
WriteEnable <= '0';
|
WriteEnable <= '0';
|
Address <= x"0011";
|
Address <= x"0111";
|
wait for 10 ns;
|
wait for 10 ns;
|
assert (DataOut = x"0012") report "unaligned 8-bit memory read is wrong" severity error;
|
assert (DataOut = x"0012") report "unaligned 8-bit memory read is wrong" severity error;
|
WriteWord <='0';
|
WriteWord <='0';
|
WriteEnable <= '1';
|
WriteEnable <= '1';
|
DataIn <= x"0056";
|
DataIn <= x"0056";
|
wait for 10 ns;
|
wait for 10 ns;
|
WriteEnable <= '0';
|
WriteEnable <= '0';
|
wait for 10 ns;
|
wait for 10 ns;
|
assert (DataOut = x"0056") report "unaligned 8 bit memory write and then read is wrong" severity error;
|
assert (DataOut = x"0056") report "unaligned 8 bit memory write and then read is wrong" severity error;
|
Address <= x"0010";
|
Address <= x"0110";
|
wait for 10 ns;
|
wait for 10 ns;
|
assert (DataOut = x"5634") report "aligned memory read after unaligned write is wrong" severity error;
|
assert (DataOut = x"5634") report "aligned memory read after unaligned write is wrong" severity error;
|
WriteEnable <= '1';
|
WriteEnable <= '1';
|
DataIn <= x"0078";
|
DataIn <= x"0078";
|
wait for 10 ns;
|
wait for 10 ns;
|
WriteEnable <= '0';
|
WriteEnable <= '0';
|
wait for 10 ns;
|
wait for 10 ns;
|
assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
|
assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;
|
|
|
|
Address <= x"0001";
|
|
WriteWord <= '0';
|
|
WriteEnable <= '1';
|
|
DataIn <= b"00000000_0011_1000";
|
|
wait for 10 ns;
|
|
Address <= x"0000";
|
|
Port0 <= "10ZZZ101";
|
|
DataIn <= x"00" & b"00_101_011";
|
|
wait for 10 ns;
|
|
WriteEnable <= '0';
|
|
wait for 10 ns;
|
|
assert(Port0 = "10101101") report "Memory mapped port does not work correctly" severity error;
|
|
assert(DataOut = x"00" & "10101101") report "Memory read of mapped port does not work correctly" severity error;
|
|
|
|
|
assert false
|
assert false
|
report "Testbench of memory completed successfully!"
|
report "Testbench of memory completed successfully!"
|
severity note;
|
severity note;
|
|
|
wait;
|
wait;
|