URL https://opencores.org/ocsvn/tinycpu/tinycpu/trunk

Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] [testbench/] [memory_tb.vhd] - Diff between revs 37 and 41

Rev 37	Rev 41
Line 118...	Line 118...
`WriteEnable <= '0';`	`WriteEnable <= '0';`
`wait for 10 ns;`	`wait for 10 ns;`
`assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;`	`assert (DataOut = x"5678") report "aligned 8-bit memory write is wrong" severity error;`

`Address <= x"0001";`	`Address <= x"0001";`
	`Port0 <= "ZZZZZZ1Z";`
	`WriteWord<='0';`
	`WriteEnable <= '1';`
	`DataIn <= x"0001";`
	`wait for 10 ns;`
	`WriteEnable <= '0';`
	`Address <= x"1234";`
	`wait for 20 ns;`
	`WriteEnable <= '1';`
	`Address <= x"0000";`
	`DataIn <= x"0001";`

	`wait for 10 ns;`
	`WriteEnable <= '0';`
	`assert(Port0(0)='1') report "port0 not right 1" severity error;`
	`wait for 10 ns;`
	`assert(DataOut(1)='1') report "port0 not right 2" severity error;`


	`wait for 10 ns;`
	`Address <= x"0001";`
`WriteWord <= '0';`	`WriteWord <= '0';`
`WriteEnable <= '1';`	`WriteEnable <= '1';`
`DataIn <= b"00000000_0011_1000";`	`DataIn <= b"00000000_0011_1000";`
`wait for 10 ns;`	`wait for 10 ns;`
`Address <= x"0000";`	`Address <= x"0000";`