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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE ieee.numeric_std.ALL;
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use work.tinycpu.all;
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ENTITY registerfile_tb IS
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ENTITY registerfile_tb IS
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END registerfile_tb;
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END registerfile_tb;
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ARCHITECTURE behavior OF registerfile_tb IS
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ARCHITECTURE behavior OF registerfile_tb IS
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-- Component Declaration for the Unit Under Test (UUT)
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-- Component Declaration for the Unit Under Test (UUT)
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component registerfile
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component registerfile
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port(
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port(
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Write1:in std_logic_vector(7 downto 0); --what should be put into the write register
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WriteEnable: in regwritetype;
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Write2: in std_logic_vector(7 downto 0);
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DataIn: in regdatatype;
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SelRead1:in std_logic_vector(3 downto 0); --select which register to read
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SelRead2: in std_logic_vector(3 downto 0); --select second register to read
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SelWrite1:in std_logic_vector(3 downto 0); --select which register to write
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SelWrite2:in std_logic_vector(3 downto 0);
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UseWrite1:in std_logic; --if the register should actually be written to
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UseWrite2: in std_logic;
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Clock:in std_logic;
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Clock:in std_logic;
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Read1:out std_logic_vector(7 downto 0); --register to be read output
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DataOut: out regdatatype
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Read2:out std_logic_vector(7 downto 0) --register to be read on second output
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);
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);
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end component;
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end component;
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--Inputs
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--Inputs
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signal Write1 : std_logic_vector(7 downto 0) := (others => '0');
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signal WriteEnable : regwritetype := (others => '0');
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signal Write2 : std_logic_vector(7 downto 0) := (others => '0');
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signal DataIn: regdatatype := (others => "00000000");
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signal SelRead1: std_logic_vector(3 downto 0) := (others => '0');
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signal SelRead2: std_logic_vector(3 downto 0) := (others => '0');
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signal SelWrite1: std_logic_vector(3 downto 0) := (others => '0');
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signal SelWrite2: std_logic_vector(3 downto 0) := (others => '0');
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signal UseWrite1: std_logic := '0';
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signal UseWrite2: std_logic := '0';
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--Outputs
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--Outputs
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signal Read1 : std_logic_vector(7 downto 0);
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signal DataOut: regdatatype := (others => "00000000");
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signal Read2 : std_logic_vector(7 downto 0);
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signal Clock: std_logic;
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signal Clock: std_logic;
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constant clock_period : time := 10 ns;
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constant clock_period : time := 10 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: registerfile PORT MAP (
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uut: registerfile PORT MAP (
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Write1 => Write1,
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WriteEnable => WriteEnable,
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Write2 => Write2,
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DataIn => DataIn,
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SelRead1 => SelRead1,
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SelRead2 => SelRead2,
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SelWrite1 => SelWrite1,
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SelWrite2 => SelWrite2,
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UseWrite1 => UseWrite1,
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UseWrite2 => UseWrite2,
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Clock => Clock,
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Clock => Clock,
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Read1 => Read1,
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DataOut => DataOut
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Read2 => Read2
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);
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);
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-- Clock process definitions
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-- Clock process definitions
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clock_process :process
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clock_process :process
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begin
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begin
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wait for 100 ns;
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wait for 100 ns;
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wait for clock_period*10;
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wait for clock_period*10;
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-- case 1
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-- case 1
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SelWrite1 <= "0000";
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WriteEnable(1) <= '1';
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Write1 <= "11110000";
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DataIn(1) <= "11110000";
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UseWrite1 <= '1';
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wait for 10 ns;
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wait for 10 ns;
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SelRead1 <= "0000";
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WriteEnable(1) <= '0';
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UseWrite1 <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (Read1="11110000") report "Storage error case 1" severity error;
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assert (DataOut(1)="11110000") report "Storage error case 1" severity error;
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-- case 2
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-- case 2
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SelWrite1 <= "1000";
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WriteEnable(5) <= '1';
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Write1 <= "11110001";
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DataIn(5) <= "11110001";
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UseWrite1 <= '1';
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wait for 10 ns;
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wait for 10 ns;
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SelRead1 <= "1000";
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WriteEnable(5) <= '0';
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UseWrite1 <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (Read1="11110001") report "Storage selector error case 2" severity error;
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assert (DataOut(5)="11110001") report "Storage selector error case 2" severity error;
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-- case 3
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-- case 3;
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SelRead1 <= "0000";
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UseWrite1 <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (Read1="11110000") report "Storage selector(remembering) error case 3" severity error;
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assert (DataOut(1)="11110000") report "Storage selector(remembering) error case 3" severity error;
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--case 4
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--case 4
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SelWrite1 <= x"0";
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DataIn(0) <= x"12";
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SelWrite2 <= x"1";
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DataIn(1) <= x"34";
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Write1 <= x"12";
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WriteEnable(0) <= '1';
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Write2 <= x"34";
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WriteEnable(1) <= '1';
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UseWrite1 <= '1';
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wait for 10 ns;
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UseWrite2 <= '1';
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DataIn(0) <= x"90";
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wait for 10 ns;
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WriteEnable(0) <= '0';
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UseWrite1 <= '0';
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WriteEnable(1) <= '0';
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UseWrite2 <= '0';
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SelRead1 <= x"0";
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SelRead2 <= x"1";
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wait for 10 ns;
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assert (Read1=x"12" and Read2=x"34") report "simultaneous write and read error case 4" severity error;
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SelWrite1 <= x"0";
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SelWrite2 <= x"0";
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Write1 <= x"ff";
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Write2 <= x"00";
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UseWrite1 <= '1';
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UseWrite2 <= '1';
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wait for 10 ns;
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SelRead1 <= x"0";
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UseWrite1 <= '0';
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UseWrite2 <= '0';
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wait for 10 ns;
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wait for 10 ns;
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assert (Read1=x"ff") report "dual-write error handling error case 5" severity error;
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assert (DataOut(0)=x"12" and DataOut(1)=x"34") report "simultaneous write and read error case 4" severity error;
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-- summary of testbench
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-- summary of testbench
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assert false
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assert false
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