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[/] [tinycpu/] [trunk/] [testbench/] [registerfile_tb.vhd] - Diff between revs 12 and 14

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Rev 12 Rev 14
Line 89... Line 89...
    WriteEnable(0) <= '0';
    WriteEnable(0) <= '0';
    WriteEnable(1) <= '0';
    WriteEnable(1) <= '0';
    wait for 10 ns;
    wait for 10 ns;
    assert (DataOut(0)=x"12" and DataOut(1)=x"34") report "simultaneous write and read error case 4" severity error;
    assert (DataOut(0)=x"12" and DataOut(1)=x"34") report "simultaneous write and read error case 4" severity error;
 
 
 
    --case 5
 
    DataIn(0) <= x"55";
 
    WriteEnable(0) <= '1';
 
    wait for 10 ns;
 
    DataIn(0) <= x"77";
 
    assert (DataOut(0)=x"55") report "Write during read error case 5" severity error;
 
    wait for 10 ns;
 
 
 
 
 
 
 
 
    -- summary of testbench
    -- summary of testbench
    assert false
    assert false

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