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[/] [tinycpu/] [trunk/] [testbench/] [top_tb.vhd] - Diff between revs 25 and 28
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| Rev 25 |
Rev 28 |
| Line 96... |
Line 96... |
wait for 10 ns;
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wait for 10 ns;
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--start the processor
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--start the processor
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Reset <= '0';
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Reset <= '0';
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wait for 30 ns; --wait 3 clock cycles for CPU to execute first instruction
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wait for 30 ns; --wait 3 clock cycles for CPU to execute first instruction
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wait for 20 ns; --wait 2 clock cycle for first instruction decode and register write to complete
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wait for 10 ns; --wait 1 clock cycle for first instruction decode
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assert(Debugr0 = x"57") report "R0 is not loaded properly for first instruction" severity error;
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assert(Debugr0 = x"57") report "R0 is not loaded properly for first instruction" severity error;
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wait for 10 ns;
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wait for 10 ns;
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assert(DebugR0 = x"F1") report "R0 is not loaded properly for second instruction" severity error;
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assert(DebugR0 = x"F1") report "R0 is not loaded properly for second instruction" severity error;
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