| Line 39... |
Line 39... |
set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C20F484C7
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set_global_assignment -name DEVICE EP2C20F484C7
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set_global_assignment -name TOP_LEVEL_ENTITY AlteraDK1
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set_global_assignment -name TOP_LEVEL_ENTITY AlteraDK1
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.0 SP1"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:59 FEBRUARY 24, 2014"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:41:59 FEBRUARY 24, 2014"
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set_global_assignment -name LAST_QUARTUS_VERSION "11.0 SP1"
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set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2"
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
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| Line 188... |
Line 188... |
set_location_assignment PIN_G12 -to uart0_txd
|
set_location_assignment PIN_G12 -to uart0_txd
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
|
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
|
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/vliwProc.vhd
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set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
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set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/statusReg.vhd
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
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set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/regSet.vhd
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7
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set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/pcReg.vhd
|
|
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/loadStore.vhd
|
|
set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/jmpExec.vhd
|
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set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/irqCntl.vhd
|
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set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/instDecoder.vhd
|
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set_global_assignment -name VHDL_FILE ../../source/vhdl/vliwProc/alu.vhd
|
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set_global_assignment -name VHDL_FILE ../../source/vhdl/timer.vhd
|
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set_global_assignment -name VHDL_FILE ../../source/vhdl/spiSlave.vhd
|
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set_global_assignment -name VHDL_FILE ../../source/vhdl/ioport.vhd
|
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set_global_assignment -name VHDL_FILE ../../source/vhdl/gendelay.vhd
|
|
set_global_assignment -name VHDL_FILE ../../source/vhdl/clock_divider.vhd
|
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set_global_assignment -name VHDL_FILE AlteraDK1.vhd
|
set_global_assignment -name VHDL_FILE AlteraDK1.vhd
|
set_global_assignment -name QIP_FILE dataMem.qip
|
set_global_assignment -name QIP_FILE dataMem.qip
|
set_global_assignment -name QIP_FILE instMem.qip
|
set_global_assignment -name QIP_FILE instMem.qip
|
set_global_assignment -name SDC_FILE AlteraDK1.sdc
|
set_global_assignment -name SDC_FILE AlteraDK1.sdc
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/vliwProc.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/statusReg.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/regSet.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/pcReg.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/loadStore.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/jmpExec.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/irqCntl.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/instDecoder.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/proc/alu.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/library/latch.vhd
|
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set_global_assignment -name VHDL_FILE ../../src/vhdl/timer.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/spiSlave.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/spiMaster.vhd
|
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set_global_assignment -name VHDL_FILE ../../src/vhdl/rstCtrl.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/ioport.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/vhdl/gendelay.vhd
|
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set_global_assignment -name VHDL_FILE ../../src/vhdl/clock_divider.vhd
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
No newline at end of file
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No newline at end of file
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