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-------------------------------------------------------------------------------
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--
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-- Design: tinyVLIW8 soft-core processor
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-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
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-- Date: 24.10.2013
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-- File: regSet.vhd
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--
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-------------------------------------------------------------------------------
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--
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-- Description : This unit is the register set unit of the 8-bit tinyVLIW8
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-- vliw processor.
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
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--
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-- This code is free software. It is licensed under the EUPL, Version 1.1
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-- or - as soon they will be approved by the European Commission - subsequent
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-- versions of the EUPL (the "License").
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-- You may redistribute this code and/or modify it under the terms of this
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-- License.
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-- You may not use this work except in compliance with the License.
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-- You may obtain a copy of the License at:
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--
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-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" basis,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity vliwProc_regSet is
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entity vliwProc_regSet is
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signal irqReg0_s : std_logic_vector(7 downto 0);
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signal irqReg0_s : std_logic_vector(7 downto 0);
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signal irqReg1_s : std_logic_vector(7 downto 0);
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signal irqReg1_s : std_logic_vector(7 downto 0);
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signal irqReg2_s : std_logic_vector(7 downto 0);
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signal irqReg2_s : std_logic_vector(7 downto 0);
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signal irqReg3_s : std_logic_vector(7 downto 0);
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signal irqReg3_s : std_logic_vector(7 downto 0);
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signal irqReg4_s : std_logic_vector(7 downto 0);
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signal irqReg5_s : std_logic_vector(7 downto 0);
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signal reg0_s : std_logic_vector(7 downto 0);
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signal reg0_s : std_logic_vector(7 downto 0);
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signal reg1_s : std_logic_vector(7 downto 0);
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signal reg1_s : std_logic_vector(7 downto 0);
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signal reg2_s : std_logic_vector(7 downto 0);
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signal reg2_s : std_logic_vector(7 downto 0);
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signal reg3_s : std_logic_vector(7 downto 0);
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signal reg3_s : std_logic_vector(7 downto 0);
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if (rst_n = '0') then
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if (rst_n = '0') then
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irqReg0_s <= (others => '0');
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irqReg0_s <= (others => '0');
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irqReg1_s <= (others => '0');
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irqReg1_s <= (others => '0');
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irqReg2_s <= (others => '0');
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irqReg2_s <= (others => '0');
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irqReg3_s <= (others => '0');
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irqReg3_s <= (others => '0');
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irqReg4_s <= (others => '0');
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irqReg5_s <= (others => '0');
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reg0_s <= (others => '0');
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reg0_s <= (others => '0');
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reg1_s <= (others => '0');
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reg1_s <= (others => '0');
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reg2_s <= (others => '0');
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reg2_s <= (others => '0');
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reg3_s <= (others => '0');
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reg3_s <= (others => '0');
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irqReg3_s <= aluRegData_s;
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irqReg3_s <= aluRegData_s;
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else
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else
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reg3_s <= aluRegData_s;
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reg3_s <= aluRegData_s;
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end if;
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end if;
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elsif (aluRegSel_s = "100") then
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elsif (aluRegSel_s = "100") then
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if (irqEn_s = '1') then
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irqReg4_s <= aluRegData_s;
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else
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reg4_s <= aluRegData_s;
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reg4_s <= aluRegData_s;
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end if;
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elsif (aluRegSel_s = "101") then
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elsif (aluRegSel_s = "101") then
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if (irqEn_s = '1') then
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irqReg5_s <= aluRegData_s;
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else
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reg5_s <= aluRegData_s;
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reg5_s <= aluRegData_s;
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end if;
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elsif (aluRegSel_s = "110") then
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elsif (aluRegSel_s = "110") then
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reg6_s <= aluRegData_s;
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reg6_s <= aluRegData_s;
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elsif (aluRegSel_s = "111") then
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elsif (aluRegSel_s = "111") then
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reg7_s <= aluRegData_s;
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reg7_s <= aluRegData_s;
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end if;
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end if;
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irqReg3_s <= ldstRegData_s;
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irqReg3_s <= ldstRegData_s;
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else
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else
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reg3_s <= ldstRegData_s;
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reg3_s <= ldstRegData_s;
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end if;
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end if;
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elsif (ldstRegSel_s = "100") then
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elsif (ldstRegSel_s = "100") then
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if (irqEn_s = '1') then
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irqReg4_s <= ldstRegData_s;
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else
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reg4_s <= ldstRegData_s;
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reg4_s <= ldstRegData_s;
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end if;
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elsif (ldstRegSel_s = "101") then
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elsif (ldstRegSel_s = "101") then
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if (irqEn_s = '1') then
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irqReg5_s <= ldstRegData_s;
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else
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reg5_s <= ldstRegData_s;
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reg5_s <= ldstRegData_s;
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end if;
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elsif (ldstRegSel_s = "110") then
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elsif (ldstRegSel_s = "110") then
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reg6_s <= ldstRegData_s;
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reg6_s <= ldstRegData_s;
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elsif (ldstRegSel_s = "111") then
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elsif (ldstRegSel_s = "111") then
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reg7_s <= ldstRegData_s;
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reg7_s <= ldstRegData_s;
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end if;
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end if;
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reg1_s;
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reg1_s;
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reg2 <= irqReg2_s when irqEn_s = '1' else
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reg2 <= irqReg2_s when irqEn_s = '1' else
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reg2_s;
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reg2_s;
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reg3 <= irqReg3_s when irqEn_s = '1' else
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reg3 <= irqReg3_s when irqEn_s = '1' else
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reg3_s;
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reg3_s;
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reg4 <= reg4_s;
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reg4 <= irqReg4_s when irqEn_s = '1' else
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reg5 <= reg5_s;
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reg4_s;
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reg5 <= irqReg5_s when irqEn_s = '1' else
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reg5_s;
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reg6 <= reg6_s;
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reg6 <= reg6_s;
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reg7 <= reg7_s;
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reg7 <= reg7_s;
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END behavior;
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END behavior;
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