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-----------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Design: tinyVLIW8 soft-core processor
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-- Design: tinyVLIW8 soft-core processor
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-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
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-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
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-- Date: 24.10.2013
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-- Date: 24.10.2013
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-- File: vliwProc.vhd
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-- File: vliwProc.vhd
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--
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--
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-----------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Description : This unit is the VLIW processor core.
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-- Description : This unit is the VLIW processor core.
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--
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--
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-----------------------------------------------------------------
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-------------------------------------------------------------------------------
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--
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--
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-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
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-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
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--
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--
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-- This code is free software. It is licensed under the EUPL, Version 1.1
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-- This code is free software. It is licensed under the EUPL, Version 1.1
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-- or - as soon they will be approved by the European Commission - subsequent
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-- or - as soon they will be approved by the European Commission - subsequent
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-- distributed under the License is distributed on an "AS IS" basis,
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-- distributed under the License is distributed on an "AS IS" basis,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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-- limitations under the License.
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--
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--
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-----------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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instMemEn_n <= instMemEn_n_s;
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instMemEn_n <= instMemEn_n_s;
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instDataIn_s <= instMemDataIn;
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instDataIn_s <= instMemDataIn;
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-- irqEn <= statusRegData_s(0);
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-- irqEn <= statusRegData_s(0);
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instMemEn_n_s <= '1' when rst_n = '0' or state_s(3) = '1' or
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instMemEn_n_s <= '1' when rst_n = '0' or state_s(3) = '1' or (stall_n_s = '0') else
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(stall_n_s = '0') else
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'0';
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'0';
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-- instMemClk_s <= '1' when state_s(0) = '1' or state_s(2) = '1' else
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-- '0';
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-- stateGen_proc : process(rst_n, instMemClk_s)
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-- begin
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-- if (rst_n = '0') then
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-- instMemEn_n_s <= '1';
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-- else
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-- if (instMemClk_s'event and instMemClk_s = '1') then
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-- instMemEn_n_s <= not(instMemEn_n_s);
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-- end if;
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-- end if;
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-- end process;
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------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------
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--
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--
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-- register Set
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-- register Set
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--
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--
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