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-------------------------------------------------------------------------------
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--
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-- Design: tinyVLIW8 soft-core processor
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-- Author: Oliver Stecklina <stecklina@ihp-microelectronics.com>
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-- Date: 24.10.2013
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-- File: sysArch.vhd
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--
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-------------------------------------------------------------------------------
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--
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-- Description : TinyVLIW8 system architecture includes processor core and
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-- GPIO, timer, and SPI periperals
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--
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-------------------------------------------------------------------------------
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--
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-- Copyright (C) 2015 IHP GmbH, Frankfurt (Oder), Germany
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--
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-- This code is free software. It is licensed under the EUPL, Version 1.1
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-- or - as soon they will be approved by the European Commission - subsequent
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-- versions of the EUPL (the "License").
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-- You may redistribute this code and/or modify it under the terms of this
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-- License.
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-- You may not use this work except in compliance with the License.
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-- You may obtain a copy of the License at:
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--
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-- http://joinup.ec.europa.eu/software/page/eupl/licence-eupl
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--
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-- Unless required by applicable law or agreed to in writing, software
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-- distributed under the License is distributed on an "AS IS" basis,
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-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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-- See the License for the specific language governing permissions and
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-- limitations under the License.
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--
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-------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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entity sysArch is
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entity sysArch is
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ioDataIn : in std_logic_vector(7 downto 0);
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ioDataIn : in std_logic_vector(7 downto 0);
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ioDataOut : out std_logic_vector(7 downto 0);
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ioDataOut : out std_logic_vector(7 downto 0);
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ioWrEn_n : out std_logic;
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ioWrEn_n : out std_logic;
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ioRdEn_n : out std_logic;
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ioRdEn_n : out std_logic;
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-- interrupt handling
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-- external interrupt handling
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irqLine : in std_logic;
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irqLine : in std_logic;
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irqLineAck : out std_logic;
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irqLineAck : out std_logic;
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-- general purpose IO
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-- general purpose IO
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gpio_in : in std_logic_vector(7 downto 0);
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gpio_in : in std_logic_vector(7 downto 0);
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MOSI : OUT STD_LOGIC; -- SPI master output, slave input
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MOSI : OUT STD_LOGIC; -- SPI master output, slave input
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MISO : IN STD_LOGIC -- SPI master input, slave output
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MISO : IN STD_LOGIC -- SPI master input, slave output
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);
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);
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END component;
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END component;
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component sha1_ex
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PORT(
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resetn : IN STD_LOGIC; -- reset the module (low active)
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clk : IN STD_LOGIC; -- clock of the sha1
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cen : IN STD_LOGIC; -- IO select low active
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wen : in std_logic; --- write enable low active
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addr : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- address signal
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d_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- data
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intr : OUT STD_LOGIC; -- signalizes if generation finished
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intra : IN STD_LOGIC; -- signalizes if generation finished
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d_out : out STD_LOGIC_VECTOR(7 DOWNTO 0) -- data
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);
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end component;
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component vliwProc
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component vliwProc
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port (
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port (
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clk : in std_logic;
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clk : in std_logic;
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instMemAddr : out std_logic_vector(10 downto 0);
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instMemAddr : out std_logic_vector(10 downto 0);
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-- spi master signals
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-- spi master signals
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signal ioSpiEn_n_s : std_logic;
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signal ioSpiEn_n_s : std_logic;
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signal spiIrq_s : std_logic;
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signal spiIrq_s : std_logic;
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signal ioDataSpi_s : std_logic_vector(7 downto 0);
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signal ioDataSpi_s : std_logic_vector(7 downto 0);
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-- sha1 signals
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signal ioSha1En_n_s : std_logic;
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signal sha1Irq_s : std_logic;
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signal ioDataSha1_s : std_logic_vector(7 downto 0);
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-- external io interface
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-- external io interface
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signal ioDataExt_s : std_logic_vector(7 downto 0);
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signal ioDataExt_s : std_logic_vector(7 downto 0);
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signal ioExtEn_n_s : std_logic;
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signal ioExtEn_n_s : std_logic;
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begin
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begin
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clk_s <= clk;
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clk_s <= clk;
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rst_n_s <= rst_n;
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rst_n_s <= rst_n;
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stall_n_s <= stall_n;
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stall_n_s <= stall_n;
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stalled_n <= stalled_n_s;
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stalled_n <= stalled_n_s;
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irqLineAck <= irqLineAck_s(0); -- export IRQ 0
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irqLineAck <= irqLineAck_s(0); -- export IRQ 0
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irqLine_s <= ioPortIrq_s & timer_irq_s & sha1Irq_s & spiIrq_s & irqLine;
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irqLine_s <= ioPortIrq_s & timer_irq_s & '0' & spiIrq_s & irqLine;
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instMemAddr <= instAddr_s;
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instMemAddr <= instAddr_s;
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instDataIn_s <= instMemDataIn;
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instDataIn_s <= instMemDataIn;
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instMemEn_n <= instEn_n_s;
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instMemEn_n <= instEn_n_s;
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dataMemWr_n <= dataWr_n_s;
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dataMemWr_n <= dataWr_n_s;
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ioDataIn_s <= ioDataGpio_s when ioPortEn_n_s = '0' else
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ioDataIn_s <= ioDataGpio_s when ioPortEn_n_s = '0' else
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ioTimerDataOut_s when ioTimerEn_n_s = '0' else
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ioTimerDataOut_s when ioTimerEn_n_s = '0' else
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ioDataSpi_s when ioSpiEn_n_s = '0' else
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ioDataSpi_s when ioSpiEn_n_s = '0' else
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ioDataSha1_s when ioSha1En_n_s = '0' else
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ioDataExt_s;
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ioDataExt_s;
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vliwProc_i : vliwProc
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vliwProc_i : vliwProc
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port map (
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port map (
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clk => clk_s,
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clk => clk_s,
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SS => spi_cs,
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SS => spi_cs,
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MOSI => spi_mosi,
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MOSI => spi_mosi,
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MISO => spi_miso
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MISO => spi_miso
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);
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);
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ioSha1En_n_s <= ioEn_n_s when ioAddr_s(7 downto 2) = "000111" else
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'1';
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sha1_i : sha1_ex
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port map (
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resetn => rst_n_s,
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clk => clk_s,
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cen => ioSha1En_n_s,
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wen => ioWr_n_s,
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addr => ioAddr_s(1 downto 0),
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d_in => ioDataOut_s,
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intr => sha1Irq_s,
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intra => irqLineAck_s(2),
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d_out => ioDataSha1_s
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);
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ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00100" else
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ioPortEn_n_s <= ioEn_n_s when ioAddr_s(7 downto 3) = "00100" else
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'1';
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'1';
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ioport_i : ioport
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ioport_i : ioport
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port map (
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port map (
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