| Line 75... |
Line 75... |
a_in : in std_logic;
|
a_in : in std_logic;
|
a_out : out std_logic
|
a_out : out std_logic
|
);
|
);
|
end component;
|
end component;
|
|
|
signal clk_s : std_logic;
|
-- signal clk_s : std_logic;
|
signal rst_n_s : std_logic;
|
signal rst_n_s : std_logic;
|
|
|
signal cnt_reg : std_logic_vector(15 downto 0); -- state counter
|
signal cnt_reg : std_logic_vector(15 downto 0); -- state counter
|
signal ifg_reg : std_logic_vector(1 downto 0);
|
signal ifg_reg : std_logic_vector(1 downto 0);
|
|
|
| Line 94... |
Line 94... |
signal divclk_s : std_logic;
|
signal divclk_s : std_logic;
|
|
|
signal clrBit_s : std_logic;
|
signal clrBit_s : std_logic;
|
signal clr_s : std_logic;
|
signal clr_s : std_logic;
|
|
|
BEGIN
|
signal rst_tar_cnt : std_logic;
|
|
|
delay_i: gendelay
|
BEGIN
|
generic map (n => 2)
|
|
port map (
|
|
a_in => clrBit_s,
|
|
a_out => clr_s
|
|
);
|
|
|
|
|
-- delay_i: gendelay
|
|
-- generic map (n => 2)
|
|
-- port map (
|
|
-- a_in => clrBit_s,
|
|
-- a_out => clr_s
|
|
-- );
|
|
clr_s <= clrBit_s;
|
rst_n_s <= rst_n;
|
rst_n_s <= rst_n;
|
clk_s <= clk;
|
-- clk_s <= clk;
|
|
|
clk_div_i : clock_divider
|
clk_div_i : clock_divider
|
generic map (n => 2)
|
generic map (n => 2)
|
port map (
|
port map (
|
inclk => clk_s,
|
inclk => clk,
|
outclk => divclk_s,
|
outclk => divclk_s,
|
|
|
div => ctl_reg(2 downto 1),
|
div => ctl_reg(2 downto 1),
|
en => ctl_reg(0)
|
en => ctl_reg(0)
|
);
|
);
|
|
|
tar_cnt : process (divclk_s, rst_n_s, clr_s) -- state counter
|
clrBit_s <= '1' when dataIn(7) = '1' and readEn_n = '0' and addr = "000" and writeEn_n = '0' else
|
|
'0';
|
|
|
|
rst_tar_cnt <='0' when rst_n_s='0' else
|
|
'0' when clrBit_s='1' else
|
|
'1';
|
|
|
|
|
|
tar_cnt : process (divclk_s, rst_tar_cnt) -- state counter
|
variable cnt: unsigned (15 downto 0);
|
variable cnt: unsigned (15 downto 0);
|
BEGIN
|
BEGIN
|
IF (rst_n_s = '0' or clr_s = '1') THEN
|
--IF (rst_n_s = '0' or clr_s = '1') THEN
|
|
IF (rst_tar_cnt='0') THEN
|
cnt := (others => '0');
|
cnt := (others => '0');
|
ELSE
|
ELSE
|
if (divclk_s'EVENT AND divclk_s = '1') THEN -- rising SCKL edge
|
if (divclk_s'EVENT AND divclk_s = '1') THEN -- rising SCKL edge
|
IF (ctl_reg(6) = '0' and cnt = cnt'high) or (ctl_reg(6) = '1' and cnt = unsigned(ccr0)) THEN
|
IF (ctl_reg(6) = '0' and cnt = cnt'high) or (ctl_reg(6) = '1' and cnt = unsigned(ccr0)) THEN
|
cnt := (others => '0');
|
cnt := (others => '0');
|
| Line 134... |
Line 145... |
END IF;
|
END IF;
|
|
|
cnt_reg <= std_logic_vector(cnt);
|
cnt_reg <= std_logic_vector(cnt);
|
END PROCESS;
|
END PROCESS;
|
|
|
irq_en : process(rst_n_s, clk_s)
|
irq_en : process(rst_n_s, clk)
|
begin
|
begin
|
IF (rst_n_s = '0') THEN
|
IF (rst_n_s = '0') THEN
|
irq_s <= '0';
|
irq_s <= '0';
|
ELSE
|
ELSE
|
if (clk_s'EVENT AND clk_s = '0') THEN -- falling SCKL edge
|
if (clk'EVENT AND clk = '0') THEN -- falling SCKL edge
|
if (irq_ack = '1') then
|
if (irq_ack = '1') then
|
irq_s <= '0';
|
irq_s <= '0';
|
else
|
else
|
if ((ctl_reg(4) = '1' and cnt_reg = ccr0 and ifg_reg(0) = '0') or (ctl_reg(5) = '1' and cnt_reg = ccr1 and ifg_reg(1) = '0')) then
|
if ((ctl_reg(4) = '1' and cnt_reg = ccr0 and ifg_reg(0) = '0') or (ctl_reg(5) = '1' and cnt_reg = ccr1 and ifg_reg(1) = '0')) then
|
irq_s <= '1';
|
irq_s <= '1';
|
| Line 199... |
Line 210... |
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
END PROCESS;
|
END PROCESS;
|
|
|
clrBit_s <= '1' when dataIn(7) = '1' and readEn_n = '0' and addr = "000" and writeEn_n = '0' else
|
|
'0';
|
|
|
|
dataOut <= '0' & ctl_reg when rst_n_s = '1' and readEn_n = '0' and addr = "000" else
|
dataOut <= '0' & ctl_reg when rst_n_s = '1' and readEn_n = '0' and addr = "000" else
|
"000000" & ifg_reg(1 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "001" else
|
"000000" & ifg_reg(1 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "001" else
|
cnt_reg(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "010" else
|
cnt_reg(7 downto 0) when rst_n_s = '1' and readEn_n = '0' and addr = "010" else
|
cnt_reg(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "011" else
|
cnt_reg(15 downto 8) when rst_n_s = '1' and readEn_n = '0' and addr = "011" else
|
