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[/] [ts7300_opencore/] [trunk/] [altera_spram_256x32.v] - Diff between revs 2 and 5

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// megafunction wizard: %ALTSYNCRAM%
 
// GENERATION: STANDARD
 
// VERSION: WM1.0
 
// MODULE: altsyncram 
 
 
 
// ============================================================
 
// File Name: altera_spram_256x32.v
 
// Megafunction Name(s):
 
//                      altsyncram
 
// ============================================================
 
// ************************************************************
 
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 
//
 
// 5.1 Build 216 03/06/2006 SP 2 SJ Web Edition
 
// ************************************************************
 
 
 
 
 
//Copyright (C) 1991-2006 Altera Corporation
 
//Your use of Altera Corporation's design tools, logic functions 
 
//and other software and tools, and its AMPP partner logic 
 
//functions, and any output files any of the foregoing 
 
//(including device programming or simulation files), and any 
 
//associated documentation or information are expressly subject 
 
//to the terms and conditions of the Altera Program License 
 
//Subscription Agreement, Altera MegaCore Function License 
 
//Agreement, or other applicable license agreement, including, 
 
//without limitation, that your use is for the sole purpose of 
 
//programming logic devices manufactured by Altera and sold by 
 
//Altera or its authorized distributors.  Please refer to the 
 
//applicable agreement for further details.
 
 
 
 
 
// synopsys translate_off
 
`timescale 1 ps / 1 ps
 
// synopsys translate_on
 
module altera_spram_256x32 (
 
        address,
 
        byteena_a,
 
        clock,
 
        data,
 
        wren,
 
        q);
 
 
 
        input   [7:0]  address;
 
        input   [3:0]  byteena_a;
 
        input     clock;
 
        input   [31:0]  data;
 
        input     wren;
 
        output  [31:0]  q;
 
 
 
        wire [31:0] sub_wire0;
 
        wire [31:0] q = sub_wire0[31:0];
 
 
 
        altsyncram      altsyncram_component (
 
                                .wren_a (wren),
 
                                .clock0 (clock),
 
                                .byteena_a (byteena_a),
 
                                .address_a (address),
 
                                .data_a (data),
 
                                .q_a (sub_wire0),
 
                                .aclr0 (1'b0),
 
                                .aclr1 (1'b0),
 
                                .q_b (),
 
                                .clocken1 (1'b1),
 
                                .clocken0 (1'b1),
 
                                .data_b (1'b1),
 
                                .rden_b (1'b1),
 
                                .address_b (1'b1),
 
                                .wren_b (1'b0),
 
                                .byteena_b (1'b1),
 
                                .addressstall_a (1'b0),
 
                                .addressstall_b (1'b0),
 
                                .clock1 (1'b1));
 
        defparam
 
                altsyncram_component.byte_size = 8,
 
                altsyncram_component.clock_enable_input_a = "BYPASS",
 
                altsyncram_component.clock_enable_output_a = "BYPASS",
 
                altsyncram_component.intended_device_family = "Cyclone II",
 
                altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
 
                altsyncram_component.lpm_type = "altsyncram",
 
                altsyncram_component.numwords_a = 256,
 
                altsyncram_component.operation_mode = "SINGLE_PORT",
 
                altsyncram_component.outdata_aclr_a = "NONE",
 
                altsyncram_component.outdata_reg_a = "UNREGISTERED",
 
                altsyncram_component.power_up_uninitialized = "FALSE",
 
                altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
 
                altsyncram_component.widthad_a = 8,
 
                altsyncram_component.width_a = 32,
 
                altsyncram_component.width_byteena_a = 4;
 
 
 
 
 
endmodule
 
 
 
// ============================================================
 
// CNX file retrieval info
 
// ============================================================
 
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
 
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
 
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
 
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
 
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1"
 
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
 
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
 
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
 
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
 
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
 
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
 
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
 
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
 
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
 
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
 
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
 
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
 
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
 
// Retrieval info: PRIVATE: Clock NUMERIC "0"
 
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
 
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
 
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
 
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
 
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
 
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
 
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
 
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
 
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
 
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
 
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
 
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "8192"
 
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
 
// Retrieval info: PRIVATE: MIFfilename STRING ""
 
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1"
 
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
 
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
 
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
 
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
 
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
 
// Retrieval info: PRIVATE: REGq NUMERIC "0"
 
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
 
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
 
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
 
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
 
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
 
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
 
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32"
 
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
 
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32"
 
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
 
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
 
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
 
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
 
// Retrieval info: PRIVATE: enable NUMERIC "0"
 
// Retrieval info: PRIVATE: rden NUMERIC "0"
 
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
 
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
 
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
 
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
 
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
 
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
 
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
 
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
 
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
 
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
 
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
 
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
 
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
 
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
 
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
 
// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL address[7..0]
 
// Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC byteena_a[3..0]
 
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
 
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
 
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
 
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren
 
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
 
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
 
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
 
// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
 
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0
 
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
 
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.v TRUE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.inc FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.cmp FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32.bsf TRUE FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32_inst.v FALSE
 
// Retrieval info: GEN_FILE: TYPE_NORMAL altera_spram_256x32_bb.v TRUE
 
 
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