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https://opencores.org/ocsvn/tsv/tsv/trunk
[/] [tsv/] [trunk/] [test/] [T001.TSV] - Diff between revs 5 and 6
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module mkExample (Empty);
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module mkExample (Empty);
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//Reg#(Bit#(8)) r <- mkReg(?); // don't-care is used for the
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//Reg#(Bit#(8)) r <- mkReg(?); // don't-care is used for the
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//Reg#(Bit#(8)) r1<- mkReg(8'h33);
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//Reg#(Bit#(8)) r1<- mkReg(8'h33);
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//Reg#(Bit#(8)) r2<- mkReg(~0);
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//Reg#(Bit#(8)) r2<- mkReg(~0);
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rule every( True ); // reset value of the Reg
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rule every0(True ); // reset value of the Reg
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$display("value is %h", r); // the value of r is displayed
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$display("value is %h", 0); // the value of r is displayed
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$display("value is %h", x); // the value of r is displayed
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endrule
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rule every1(True ); // reset value of the Reg
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$display("value is %h", 1, 2, x); // the value of r is displayed
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endrule
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endmodule
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module [M1] mkExample1 (Empty);
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rule every2; // reset value of the Reg
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$display("OK?");
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endrule
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endrule
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endmodule
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endmodule
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