URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_alu.v] - Diff between revs 2 and 68

Rev 2	Rev 68
Line 151...	Line 151...
`//`	`//`
`// inc`	`// inc`
`//`	`//`
`wire [15:0] inc, dec;`	`wire [15:0] inc, dec;`


`oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));`	`oc8051_multiply oc8051_mul1(.clk(clk), .rst(rst), .enable(enable_mul), .src1(src1), .src2(src2), .des1(mulsrc1), .des2(mulsrc2), .desOv(mulOv));`







`oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));`	`oc8051_divide oc8051_div1(.clk(clk), .rst(rst), .enable(enable_div), .src1(src1), .src2(src2), .des1(divsrc1), .des2(divsrc2), .desOv(divOv));`

`/* Add */`	`/* Add */`
`assign add1 = {1'b0,src1[3:0]};`	`assign add1 = {1'b0,src1[3:0]};`
`assign add2 = {1'b0,src2[3:0]};`	`assign add2 = {1'b0,src2[3:0]};`