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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_decoder.v] - Diff between revs 57 and 76

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//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
////  8051 core decoder                                           ////
////  8051 core decoder                                           ////
////                                                              ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
//// http://www.opencores.org/cores/turb08051/                    ////
////                                                              ////
////                                                              ////
////  Description                                                 ////
////  Description                                                 ////
////   Main 8051 core module. decodes instruction and creates     ////
////   Main 8051 core module. decodes instruction and creates     ////
////   control sigals.                                            ////
////   control sigals.                                            ////
////                                                              ////
////                                                              ////
////  To Do:                                                      ////
////  To Do:                                                      ////
////   optimize state machine, especially IDS ASS and AS3         ////
////   optimize state machine, especially IDS ASS and AS3         ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Simon Teran, simont@opencores.org                     ////
 
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
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// Revision 1.11  2002/09/30 17:33:59  simont
// Revision 1.11  2002/09/30 17:33:59  simont
// prepared header
// prepared header
//
//
//
//
 
 
// synopsys translate_off
`include "top_defines.v"
`include "oc8051_timescale.v"
 
// synopsys translate_on
 
 
 
`include "oc8051_defines.v"
 
 
 
 
 
module oc8051_decoder (clk, rst, op_in, op1_c,
module oc8051_decoder (clk, rst, op_in, op1_c,
  ram_rd_sel_o, ram_wr_sel_o,
  ram_rd_sel_o, ram_wr_sel_o,
  bit_addr, wr_o, wr_sfr_o,
  bit_addr, wr_o, wr_sfr_o,

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