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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 core decoder ////
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//// 8051 core decoder ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/turb08051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Main 8051 core module. decodes instruction and creates ////
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//// Main 8051 core module. decodes instruction and creates ////
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//// control sigals. ////
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//// control sigals. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// optimize state machine, especially IDS ASS and AS3 ////
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//// optimize state machine, especially IDS ASS and AS3 ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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// Revision 1.11 2002/09/30 17:33:59 simont
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// Revision 1.11 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_off
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`include "top_defines.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_decoder (clk, rst, op_in, op1_c,
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module oc8051_decoder (clk, rst, op_in, op1_c,
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ram_rd_sel_o, ram_wr_sel_o,
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ram_rd_sel_o, ram_wr_sel_o,
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bit_addr, wr_o, wr_sfr_o,
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bit_addr, wr_o, wr_sfr_o,
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