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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// 8051 indirect address ////
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//// 8051 indirect address ////
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//// ////
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//// ////
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//// This file is part of the 8051 cores project ////
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//// This file is part of the 8051 cores project ////
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//// http://www.opencores.org/cores/8051/ ////
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//// http://www.opencores.org/cores/turb08051/ ////
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//// ////
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//// ////
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//// Description ////
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//// Description ////
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//// Contains ragister 0 and register 1. used for indirrect ////
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//// Contains ragister 0 and register 1. used for indirrect ////
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//// addressing. ////
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//// addressing. ////
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//// ////
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//// ////
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//// To Do: ////
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//// To Do: ////
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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Simon Teran, simont@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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// Revision 1.4 2002/09/30 17:33:59 simont
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// Revision 1.4 2002/09/30 17:33:59 simont
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// prepared header
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// prepared header
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//
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//
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
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module oc8051_indi_addr (clk, rst, wr_addr, data_in, wr, wr_bit, ri_out, sel, bank);
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//
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//
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