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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_ram_256x8_two_bist.v] - Diff between revs 2 and 68

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Rev 2	Rev 68
Line 119...	Line 119...

`defparam`	`defparam`
`xilinx_ram.dwidth = 8,`	`xilinx_ram.dwidth = 8,`
`xilinx_ram.awidth = 8;`	`xilinx_ram.awidth = 8;`

`else	`elsif OC8051_RAM_VIRTUALSILICON

`ifdef OC8051_RAM_VIRTUALSILICON	`elsif OC8051_RAM_ACTEL

`else	`oc8051_actel_ram_256x8 oc8051_ram1(`
	`.RWCLK ( clk ),`
	`.RESET ( rst ),`
	`.REN ( rd_en ),`
	`.RADDR ( rd_addr ),`
	`.RD ( rd_data ),`

	`.WEN ( wr ),`
	`.WADDR ( wr_addr ),`
	`.WD ( wr_data )`
	`);`

`ifdef OC8051_RAM_GENERIC
	`elsif OC8051_RAM_GENERIC

`generic_dpram #(8, 8) oc8051_ram1(`	`generic_dpram #(8, 8) oc8051_ram1(`
`.rclk ( clk ),`	`.rclk ( clk ),`
`.rrst ( rst ),`	`.rrst ( rst ),`
`.rce ( rd_en ),`	`.rce ( rd_en ),`
Line 170...	Line 181...
`else if ((wr_addr==rd_addr) & wr & rd_en)`	`else if ((wr_addr==rd_addr) & wr & rd_en)`
`rd_data <= #1 wr_data;`	`rd_data <= #1 wr_data;`
`else if (rd_en)`	`else if (rd_en)`
`rd_data <= #1 buff[rd_addr];`	`rd_data <= #1 buff[rd_addr];`
`end`	`end`
`endif //OC8051_RAM_GENERIC
`endif //OC8051_RAM_VIRTUALSILICON
`endif //OC8051_RAM_XILINX	`endif //OC8051_RAM_XILINX

`endmodule`	`endmodule`

`No newline at end of file`	`No newline at end of file`

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