OpenCores

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`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// 8051 cores top level module ////`	`//// 8051 cores top level module ////`
`//// ////`	`//// ////`
`//// This file is part of the 8051 cores project ////`	`//// This file is part of the 8051 cores project ////`
`//// http://www.opencores.org/cores/8051/ ////`	`//// http://www.opencores.org/cores/turbo8051/ ////`
`//// ////`	`//// ////`
`//// Description ////`	`//// Description ////`
`//// 8051 definitions. ////`	`//// 8051 definitions. ////`
`//// ////`	`//// ////`
`//// To Do: ////`	`//// To Do: ////`
`//// nothing ////`	`//// nothing ////`
`//// ////`	`//// ////`
`//// Author(s): ////`	`//// Author(s): ////`
`//// - Simon Teran, simont@opencores.org ////`	`//// - Simon Teran, simont@opencores.org ////`
	`//// - Dinesh Annayya, dinesha@opencores.org ////`
`//// ////`	`//// ////`
`//////////////////////////////////////////////////////////////////////`	`//////////////////////////////////////////////////////////////////////`
`//// ////`	`//// ////`
`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`	`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
`//// ////`	`//// ////`
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`// Revision 1.13 2002/09/30 17:33:59 simont`	`// Revision 1.13 2002/09/30 17:33:59 simont`
`// prepared header`	`// prepared header`
`//`	`//`
`//`	`//`

`// synopsys translate_off`
`include "oc8051_timescale.v"
`// synopsys translate_on`

`include "oc8051_defines.v"	`include "top_defines.v"

`module oc8051_top (wb_rst_i, wb_clk_i,`	`module oc8051_top (wb_rst_i, wb_clk_i,`
`//interface to instruction rom`	`//interface to instruction rom`
`wbi_adr_o,`	`wbi_adr_o,`
`wbi_dat_i,`	`wbi_dat_i,`
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`);`	`);`




`ifdef OC8051_CACHE


`oc8051_icache oc8051_icache1(`
`.rst (wb_rst_i ),`
`.clk (wb_clk_i ),`
`// cpu`
`.adr_i (iadr_o ),`
`.dat_o (idat_i ),`
`.stb_i (istb_o ),`
`.ack_o (iack_i ),`
`.cyc_i (icyc_o ),`
`// pins`
`.dat_i (wbi_dat_i ),`
`.stb_o (wbi_stb_o ),`
`.adr_o (wbi_adr_o ),`
`.ack_i (wbi_ack_i ),`
`.cyc_o (wbi_cyc_o )`
`ifdef OC8051_BIST
`,`
`.scanb_rst (scanb_rst ),`
`.scanb_clk (scanb_clk ),`
`.scanb_si (scanb_si ),`
`.scanb_so (scanb_soi ),`
`.scanb_en (scanb_en )`
`endif
`);`

`defparam oc8051_icache1.ADR_WIDTH = 6; // cache address wihth`
`defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)`
`defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH`
`defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)`



`ifdef OC8051_SIMULATION

`initial`
`begin`
`#1`
`$display("\t * ");`
`$display("\t * External rom interface: cache");`
`$display("\t * ");`
`end`

`endif



`//`
`// no cache`
`//`
`else

`ifdef OC8051_BIST	`ifdef OC8051_BIST
`assign scanb_soi=scanb_si;`	`assign scanb_soi=scanb_si;`
`endif	`endif

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`endif	`endif


`endif	`endif

`endif


`// synopsys translate_off`	`// synopsys translate_off`
`// Debug Purpose only`	`// Debug Purpose only`
`// Stack Pointer Push & Pop analysis`	`// Stack Pointer Push & Pop analysis`
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`end`	`end`

`// synopsys translate_on`	`// synopsys translate_on`

`endmodule`	`endmodule`
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`No newline at end of file`	`No newline at end of file`

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//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

////  8051 cores top level module                                 ////

////  8051 cores top level module                                 ////

////                                                              ////

////                                                              ////

////  This file is part of the 8051 cores project                 ////

////  This file is part of the 8051 cores project                 ////

////  http://www.opencores.org/cores/8051/                        ////

////  http://www.opencores.org/cores/turbo8051/                   ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Description                                                 ////

////  8051 definitions.                                           ////

////  8051 definitions.                                           ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////  To Do:                                                      ////

////    nothing                                                   ////

////    nothing                                                   ////

////                                                              ////

////                                                              ////

////  Author(s):                                                  ////

////  Author(s):                                                  ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Simon Teran, simont@opencores.org                     ////

////      - Dinesh Annayya, dinesha@opencores.org                 ////

////                                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////

////                                                              ////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

////                                                              ////

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// Revision 1.13  2002/09/30 17:33:59  simont

// Revision 1.13  2002/09/30 17:33:59  simont

// prepared header

// prepared header

//

//

//

//

// synopsys translate_off

`include "oc8051_timescale.v"

// synopsys translate_on

`include "oc8051_defines.v"

`include "top_defines.v"

module oc8051_top (wb_rst_i, wb_clk_i,

module oc8051_top (wb_rst_i, wb_clk_i,

//interface to instruction rom

//interface to instruction rom

                wbi_adr_o,

                wbi_adr_o,

                wbi_dat_i,

                wbi_dat_i,

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);

);

`ifdef OC8051_CACHE

  oc8051_icache oc8051_icache1(

          .rst                (wb_rst_i           ),

          .clk                (wb_clk_i           ),

  // cpu

          .adr_i              (iadr_o             ),

          .dat_o              (idat_i             ),

          .stb_i              (istb_o             ),

          .ack_o              (iack_i             ),

          .cyc_i              (icyc_o             ),

  // pins

          .dat_i              (wbi_dat_i          ),

          .stb_o              (wbi_stb_o          ),

          .adr_o              (wbi_adr_o          ),

          .ack_i              (wbi_ack_i          ),

          .cyc_o              (wbi_cyc_o          )

`ifdef OC8051_BIST

          .scanb_rst          (scanb_rst          ),

          .scanb_clk          (scanb_clk          ),

          .scanb_si           (scanb_si           ),

          .scanb_so           (scanb_soi          ),

          .scanb_en           (scanb_en           )

`endif

);

  defparam oc8051_icache1.ADR_WIDTH = 6;  // cache address wihth

  defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)

  defparam oc8051_icache1.BL_NUM = 15; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH

  defparam oc8051_icache1.CACHE_RAM = 64; // cache ram x 32 (2^ADR_WIDTH)

  `ifdef OC8051_SIMULATION

    initial

    begin

#1

      $display("\t * ");

      $display("\t * External rom interface: cache");

      $display("\t * ");

end

  `endif

//

//    no cache

//

`else

  `ifdef OC8051_BIST

  `ifdef OC8051_BIST

       assign scanb_soi=scanb_si;

       assign scanb_soi=scanb_si;

  `endif

  `endif

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  `endif

  `endif

  `endif

  `endif

`endif

// synopsys translate_off

// synopsys translate_off

// Debug Purpose only

// Debug Purpose only

// Stack Pointer Push & Pop analysis

// Stack Pointer Push & Pop analysis

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end

end

// synopsys translate_on

// synopsys translate_on

endmodule

endmodule

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[/] [turbo8051/] [trunk/] [rtl/] [8051/] [oc8051_top.v] - Diff between revs 68 and 76