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Line 42... |
//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module clkgen (
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module clkgen (
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reset_n ,
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reset_n ,
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fastsim_mode ,
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fastsim_mode ,
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mastermode ,
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xtal_clk ,
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xtal_clk ,
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clkout ,
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clkout ,
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gen_resetn ,
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gen_resetn ,
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gen_reset ,
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risc_reset ,
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app_clk ,
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app_clk ,
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uart_ref_clk
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uart_ref_clk
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);
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);
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input reset_n ; // Async reset signal
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input reset_n ; // Async reset signal
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input fastsim_mode ; // fast sim mode = 1
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input fastsim_mode ; // fast sim mode = 1
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input mastermode ; // 1 : Risc master mode
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input xtal_clk ; // Xtal clock-25Mhx
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input xtal_clk ; // Xtal clock-25Mhx
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output clkout ; // clock output, 250Mhz
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output clkout ; // clock output, 250Mhz
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output gen_resetn ; // internally generated reset
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output gen_resetn ; // internally generated reset
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output gen_reset ; // internally generated reset
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output risc_reset ; // internally generated reset
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output app_clk ; // application clock
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output app_clk ; // application clock
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output uart_ref_clk ; // uart 16x Ref clock
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output uart_ref_clk ; // uart 16x Ref clock
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wire hard_reset_st ;
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wire hard_reset_st ;
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wire configure_st ;
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wire configure_st ;
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wire wait_pll_st ;
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wire wait_pll_st ;
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wire run_st ;
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wire run_st ;
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wire slave_run_st ;
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reg pll_done ;
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reg pll_done ;
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reg [11:0] pll_count ;
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reg [11:0] pll_count ;
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reg [1:0] clkgen_ps ;
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reg [2:0] clkgen_ps ;
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reg gen_resetn ; // internally generated reset
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reg gen_resetn ; // internally generated reset
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reg gen_reset ; // internally generated reset
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reg risc_reset ; // internally generated reset
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assign clkout = app_clk;
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assign clkout = app_clk;
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wire pllout;
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wire pllout;
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/***********************************************
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/***********************************************
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Line 135... |
************************************************/
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************************************************/
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always @(posedge xtal_clk or negedge reset_n )
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always @(posedge xtal_clk or negedge reset_n )
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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gen_resetn <= 0;
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gen_resetn <= 0;
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gen_reset <= 1;
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risc_reset <= 1;
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end else if(run_st ) begin
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end else if(run_st ) begin
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gen_resetn <= 1;
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gen_resetn <= 1;
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gen_reset <= 0;
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risc_reset <= 0;
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end else if(slave_run_st ) begin
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gen_resetn <= 1;
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risc_reset <= 1; // Keet Risc in Reset
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end else begin
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end else begin
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gen_resetn <= 0;
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gen_resetn <= 0;
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gen_reset <= 1;
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risc_reset <= 1;
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end
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end
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end
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end
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/****************************************
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/****************************************
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Reset State Machine
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Reset State Machine
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****************************************/
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****************************************/
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/*****************************************
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/*****************************************
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Define Clock Gen stat machine state
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Define Clock Gen stat machine state
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*****************************************/
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*****************************************/
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`define HARD_RESET 2'b00
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`define HARD_RESET 3'b000
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`define CONFIGURE 2'b01
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`define CONFIGURE 3'b001
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`define WAIT_PLL 2'b10
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`define WAIT_PLL 3'b010
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`define RUN 2'b11
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`define RUN 3'b011
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`define SLAVE_RUN 3'b100
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assign hard_reset_st = (clkgen_ps == `HARD_RESET);
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assign hard_reset_st = (clkgen_ps == `HARD_RESET);
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assign configure_st = (clkgen_ps == `CONFIGURE);
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assign configure_st = (clkgen_ps == `CONFIGURE);
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assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
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assign wait_pll_st = (clkgen_ps == `WAIT_PLL);
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assign run_st = (clkgen_ps == `RUN);
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assign run_st = (clkgen_ps == `RUN);
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assign slave_run_st = (clkgen_ps == `SLAVE_RUN);
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always @(posedge xtal_clk or negedge reset_n)
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always @(posedge xtal_clk or negedge reset_n)
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begin
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begin
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if (!reset_n) begin
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if (!reset_n) begin
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clkgen_ps <= `HARD_RESET;
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clkgen_ps <= `HARD_RESET;
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Line 181... |
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`CONFIGURE:
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`CONFIGURE:
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clkgen_ps <= `WAIT_PLL;
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clkgen_ps <= `WAIT_PLL;
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`WAIT_PLL:
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`WAIT_PLL:
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if (pll_done)
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if (pll_done) begin
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if ( mastermode )
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clkgen_ps <= `RUN;
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clkgen_ps <= `RUN;
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else
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clkgen_ps <= `SLAVE_RUN;
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end
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endcase
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endcase
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end
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end
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end
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end
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