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https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
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| Rev 25 |
Rev 57 |
| Line 81... |
Line 81... |
assign clkout = app_clk;
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assign clkout = app_clk;
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wire pllout;
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wire pllout;
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/***********************************************
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/***********************************************
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Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
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Alternal PLL pr-programmed for xtal: 25Mhz , clkout 250Mhz
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*********************************************************/
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*********************************************************/
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/*******************
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altera_stargate_pll u_pll (
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. areset (!reset_n ),
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. inclk0 (xtal_clk),
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. c0 (pllout),
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. locked ()
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);
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*************************/
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altera_stargate_pll u_pll (
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assign pllout = xtal_clk;
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. areset (!reset_n ),
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. inclk0 (xtal_clk),
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. c0 (pllout),
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. locked ()
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);
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//---------------------------------------------
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//---------------------------------------------
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//
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//
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// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
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// 100us use 25.000 Mhz clock, counter = 2500(0x9C4)
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| Line 196... |
Line 197... |
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//----------------------------------
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//----------------------------------
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// Generate Application clock 125Mhz
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// Generate Application clock 125Mhz
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//----------------------------------
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//----------------------------------
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clk_ctl #(2) u_appclk (
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clk_ctl #(1) u_appclk (
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// Outputs
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// Outputs
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.clk_o (app_clk),
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.clk_o (app_clk),
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// Inputs
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// Inputs
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.mclk (pllout),
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.mclk (pllout),
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.reset_n (gen_resetn),
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.reset_n (gen_resetn),
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| Line 208... |
Line 209... |
);
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);
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//----------------------------------
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//----------------------------------
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// Generate Uart Ref Clock clock 50Mhz
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// Generate Uart Ref Clock clock 50Mhz
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// 200Mhz/(2+0) = 50Mhz
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// 250Mhz/(2+3) = 50Mhz
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// 250Mhz/(2+3) = 50Mhz
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//----------------------------------
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//----------------------------------
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clk_ctl #(3) u_uart_clk (
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clk_ctl #(2) u_uart_clk (
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// Outputs
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// Outputs
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.clk_o (uart_ref_clk),
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.clk_o (uart_ref_clk),
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// Inputs
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// Inputs
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.mclk (pllout ),
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.mclk (pllout ),
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.reset_n (gen_resetn ),
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.reset_n (gen_resetn ),
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.clk_div_ratio (3'b011 )
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.clk_div_ratio (3'b000 )
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);
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);
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endmodule
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endmodule
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