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`include "top_defines.v"
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module digital_core (
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reset_n ,
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scan_mode ,
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scan_enable ,
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fastsim_mode ,
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mastermode ,
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xtal_clk ,
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clkout ,
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reset_out_n ,
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// Reg Bus Interface Signal
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ext_reg_cs ,
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ext_reg_tid ,
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ext_reg_wr ,
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ext_reg_addr ,
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ext_reg_wdata ,
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ext_reg_be ,
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// Outputs
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ext_reg_rdata ,
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ext_reg_ack ,
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// Line Side Interface TX Path
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phy_tx_en ,
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phy_txd ,
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phy_tx_clk ,
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// Line Side Interface RX Path
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phy_rx_clk ,
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phy_rx_dv ,
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phy_rxd ,
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//MDIO interface
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mdio_clk ,
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mdio_in ,
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mdio_out ,
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mdio_out_en ,
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// UART Line Interface
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si ,
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so ,
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spi_sck ,
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spi_so ,
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spi_si ,
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spi_cs_n ,
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// External ROM interface
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wb_xrom_adr ,
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wb_xrom_ack ,
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wb_xrom_err ,
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wb_xrom_wr ,
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wb_xrom_rdata ,
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wb_xrom_wdata ,
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wb_xrom_stb ,
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wb_xrom_cyc ,
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// External RAM interface
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wb_xram_adr ,
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wb_xram_ack ,
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wb_xram_err ,
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wb_xram_wr ,
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wb_xram_be ,
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wb_xram_rdata ,
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wb_xram_wdata ,
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wb_xram_stb ,
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wb_xram_cyc,
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ea_in
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);
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//----------------------------------------
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// Global Clock Defination
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//----------------------------------------
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input reset_n ; // Active Low Reset
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input scan_mode ; // scan mode
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input scan_enable ; // scan enable
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input fastsim_mode ; // Fast Sim Mode
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input mastermode ; // 1 : Risc master mode
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input xtal_clk ; // xtal clock 25Mhz
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output clkout ; // clock output
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output reset_out_n ; // clock output
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//---------------------------------
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// Reg Bus Interface Signal
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//---------------------------------
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input ext_reg_cs ;
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input ext_reg_wr ;
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input [3:0] ext_reg_tid ;
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input [14:0] ext_reg_addr ;
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input [31:0] ext_reg_wdata ;
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input [3:0] ext_reg_be ;
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// Outputs
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output [31:0] ext_reg_rdata ;
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output ext_reg_ack ;
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//----------------------------------------
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// MAC Line Side Interface TX Path
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//----------------------------------------
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output phy_tx_en ; // MAC Tx Enable
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output [7:0] phy_txd ; // MAC Tx Data
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input phy_tx_clk ; // MAC Tx Clock
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//----------------------------------------
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// MAC Line Side Interface RX Path
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//----------------------------------------
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input phy_rx_clk ; // MAC Rx Clock
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input phy_rx_dv ; // MAC Rx Dv
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input [7:0] phy_rxd ; // MAC Rxd
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//----------------------------------------
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// MDIO interface
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//----------------------------------------
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output mdio_clk ; // MDIO Clock
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input mdio_in ; // MDIO Data
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output mdio_out ; // MDIO Data
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output mdio_out_en ; // MDIO Data
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//----------------------------------------
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// UART Line Interface
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//----------------------------------------
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input si ; // serial in
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output so ; // serial out
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//----------------------------------------
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// SPI Line Interface
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//----------------------------------------
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output spi_sck ; // clock
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output spi_so ; // data out
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input spi_si ; // data in
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output [3:0] spi_cs_n ; // chip select
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//----------------------------------------
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// 8051 core ROM related signals
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//---------------------------------------
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output [15:0] wb_xrom_adr ; // instruction address
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input wb_xrom_ack ; // instruction acknowlage
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output wb_xrom_err ; // instruction error
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output wb_xrom_wr ; // instruction error
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input [31:0] wb_xrom_rdata ; // rom data input
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output [31:0] wb_xrom_wdata ; // rom data input
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output wb_xrom_stb ; // instruction strobe
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output wb_xrom_cyc ; // instruction cycle
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//----------------------------------------
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// 8051 core RAM related signals
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//---------------------------------------
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output [15:0] wb_xram_adr ; // data-ram address
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input wb_xram_ack ; // data-ram acknowlage
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output wb_xram_err ; // data-ram error
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output wb_xram_wr ; // data-ram error
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output [3:0] wb_xram_be ; // Byte enable
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input [31:0] wb_xram_rdata ; // ram data input
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output [31:0] wb_xram_wdata ; // ram data input
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output wb_xram_stb ; // data-ram strobe
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output wb_xram_cyc ; // data-ram cycle
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input ea_in ; // input for external access (ea signal)
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// ea=0 program is in external rom
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// ea=1 program is in internal rom
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//---------------------------------------------
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// 8051 Instruction ROM interface
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//---------------------------------------------
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wire [15:0] wbi_risc_adr;
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wire [31:0] wbi_risc_rdata;
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//-----------------------------
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// MAC Related wire Decleration
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//-----------------------------
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wire [8:0] app_rxfifo_rddata_o ;
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wire [31:0] app_rx_desc_data ;
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wire mdio_out_en ;
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wire mdio_out ;
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wire gen_resetn ;
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//---------------------------------------------
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// 8051 Instruction RAM interface
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//---------------------------------------------
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wire [15:0] wbd_risc_adr ;
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wire [7:0] wbd_risc_rdata ;
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wire [7:0] wbd_risc_wdata ;
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wire [14:0] reg_mac_addr ;
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wire [31:0] reg_mac_wdata ;
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wire [3:0] reg_mac_be ;
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wire [31:0] reg_mac_rdata ;
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wire reg_mac_ack ;
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wire [14:0] reg_uart_addr ;
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wire [31:0] reg_uart_wdata ;
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wire [3:0] reg_uart_be ;
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wire [31:0] reg_uart_rdata ;
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wire reg_uart_ack ;
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wire [14:0] reg_spi_addr ;
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wire [31:0] reg_spi_wdata ;
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wire [3:0] reg_spi_be ;
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wire [31:0] reg_spi_rdata ;
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wire reg_spi_ack ;
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wire [3:0] wb_xrom_be ;
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wire [3:0] wb_xram_be ;
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wire [7:0] p0 ;
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wire [7:0] p1 ;
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wire [7:0] p2 ;
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wire [7:0] p3 ;
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wire [3:0] wbgt_taddr ;
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wire [31:0] wbgt_din ;
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wire [31:0] wbgt_dout ;
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wire [12:0] wbgt_addr ;
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wire [3:0] wbgt_be ;
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wire wbgt_we ;
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wire wbgt_ack ;
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wire wbgt_stb ;
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wire wbgt_cyc ;
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wire [3:0] wbgr_taddr ;
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wire [31:0] wbgr_din ;
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wire [31:0] wbgr_dout ;
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wire [12:0] wbgr_addr ;
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wire [3:0] wbgr_be ;
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wire wbgr_we ;
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wire wbgr_ack ;
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wire wbgr_stb ;
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wire wbgr_cyc ;
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wire [8:0] app_txfifo_wrdata_i;
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wire [15:0] app_txfifo_addr;
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wire [15:0] app_rxfifo_addr;
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wire [3:0] tx_qcnt ;
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wire [3:0] rx_qcnt ;
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wire tx_q_empty = (tx_qcnt == 0);
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wire rx_q_empty = (rx_qcnt == 0);
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wire [31:0] reg_rdata = (reg_mac_ack) ? reg_mac_rdata :
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(reg_uart_ack) ? reg_uart_rdata :
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(reg_spi_ack) ? reg_spi_rdata : 'h0;
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wire reg_ack = reg_mac_ack | reg_uart_ack | reg_spi_ack;
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assign reset_out_n = gen_resetn;
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assign wb_xram_adr[15] = 0;
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assign wb_xram_adr[1:0] = 2'b00;
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assign wb_xrom_adr[15:13] = 0;
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wire [9:0] cfg_tx_buf_qbase_addr;
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wire [9:0] cfg_rx_buf_qbase_addr;
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// QCounter Inc/dec generation
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wire tx_qcnt_inc = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
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wire tx_qcnt_dec = (cfg_tx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
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wire rx_qcnt_inc = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
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wire rx_qcnt_dec = (cfg_rx_buf_qbase_addr == wb_xram_adr[15:6]) & wb_xram_stb & !wb_xram_wr & wb_xram_ack && (wb_xram_be[3] == 1'b1);
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assign reg_mac_addr[1:0] = 2'b0;
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assign reg_uart_addr[1:0] = 2'b0;
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assign reg_spi_addr[1:0] = 2'b0;
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//-------------------------------------------
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// clock-gen instantiation
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//-------------------------------------------
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clkgen u_clkgen (
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. reset_n (reset_n ),
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. fastsim_mode (fastsim_mode ),
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. mastermode (mastermode ),
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. xtal_clk (xtal_clk ),
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. clkout (clkout ),
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. gen_resetn (gen_resetn ),
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. risc_reset (risc_reset ),
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. app_clk (app_clk ),
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. uart_ref_clk (uart_clk_16x )
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);
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//--------------------------------------------------------------
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// Target ID Mapping
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// 4'b0100 -- MAC core
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// 4'b0011 -- UART
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// 4'b0010 -- SPI core
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// 4'b0001 -- External RAM
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// 4'b0000 -- External ROM
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//--------------------------------------------------------------
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wire [31:0] wb_master2_rdata;
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wire [3:0] wb_master2_be = (wbd_risc_adr[1:0] == 2'b00) ? 4'b0001:
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(wbd_risc_adr[1:0] == 2'b01) ? 4'b0010:
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(wbd_risc_adr[1:0] == 2'b10) ? 4'b0100: 4'b1000;
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assign wbd_risc_rdata = (wbd_risc_adr[1:0] == 2'b00) ? wb_master2_rdata[7:0]:
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(wbd_risc_adr[1:0] == 2'b01) ? wb_master2_rdata[15:8]:
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(wbd_risc_adr[1:0] == 2'b10) ? wb_master2_rdata[23:16]:
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wb_master2_rdata[31:24];
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//------------------------------
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// RISC Data Memory Map
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// 0x0000 to 0x7FFFF - Data Memory
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// 0x8000 to 0x8FFF - SPI
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// 0x9000 to 0x9FFF - UART
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// 0xA000 to 0xAFFF - MAC Core
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//-----------------------------
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//
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wire [3:0] wbd_tar_id = (wbd_risc_adr[15] == 1'b0 ) ? 4'b0001 :
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(wbd_risc_adr[15:12] == 4'b1000 ) ? 4'b0010 :
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(wbd_risc_adr[15:12] == 4'b1001 ) ? 4'b0011 : 4'b0100;
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wb_crossbar #(5,5,32,4,13,4) u_wb_crossbar (
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.rst_n (gen_resetn ),
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.clk (app_clk ),
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// Master Interface Signal
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.wbd_taddr_master ({4'b0000,
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wbd_tar_id,
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ext_reg_tid,
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wbgt_taddr,
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wbgr_taddr}),
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.wbd_din_master ({32'h0 ,
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{wbd_risc_wdata[7:0],
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wbd_risc_wdata[7:0],
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wbd_risc_wdata[7:0],
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wbd_risc_wdata[7:0]},
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ext_reg_wdata,
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wbgt_din,
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wbgr_din}
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),
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.wbd_dout_master ({wbi_risc_rdata,
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wb_master2_rdata,
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ext_reg_rdata,
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wbgt_dout,
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wbgr_dout}
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),
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.wbd_adr_master ({wbi_risc_adr[12:0],
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wbd_risc_adr[14:2],
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ext_reg_addr[14:2],
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wbgt_addr,
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wbgr_addr}
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),
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.wbd_be_master ({4'b1111,
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wb_master2_be,
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ext_reg_be,
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wbgt_be,
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wbgr_be}
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),
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.wbd_we_master ({1'b0,wbd_risc_we,ext_reg_wr,
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wbgt_we,wbgr_we} ),
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.wbd_ack_master ({wbi_risc_ack,
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wbd_risc_ack,
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ext_reg_ack,
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wbgt_ack,
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wbgr_ack} ),
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.wbd_stb_master ({wbi_risc_stb,
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wbd_risc_stb,
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ext_reg_cs,
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wbgt_stb,
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wbgr_stb} ),
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.wbd_cyc_master ({wbi_risc_stb|wbi_risc_ack,
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wbd_risc_stb|wbd_risc_ack,
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ext_reg_cs|ext_reg_ack,
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wbgt_cyc,wbgr_cyc}),
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.wbd_err_master (),
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.wbd_rty_master (),
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// Slave Interface Signal
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.wbd_din_slave ({
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reg_mac_wdata,
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reg_uart_wdata,
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reg_spi_wdata,
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wb_xram_wdata,
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wb_xrom_wdata
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}),
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.wbd_dout_slave ({
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reg_mac_rdata,
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reg_uart_rdata,
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reg_spi_rdata,
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{wb_xram_rdata},
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wb_xrom_rdata
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}),
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.wbd_adr_slave ({reg_mac_addr[14:2],
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reg_uart_addr[14:2],
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reg_spi_addr[14:2],
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wb_xram_adr[14:2],
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wb_xrom_adr[12:0]}
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),
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.wbd_be_slave ({reg_mac_be,
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reg_uart_be,
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reg_spi_be,
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wb_xram_be,
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wb_xrom_be}
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),
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.wbd_we_slave ({reg_mac_wr,
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reg_uart_wr,
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reg_spi_wr,
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wb_xram_wr,
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wb_xrom_wr
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}),
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.wbd_ack_slave ({reg_mac_ack,
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reg_uart_ack,
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reg_spi_ack,
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wb_xram_ack,
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wb_xrom_ack
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}),
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.wbd_stb_slave ({reg_mac_cs,
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reg_uart_cs,
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reg_spi_cs,
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wb_xram_stb,
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wb_xrom_stb
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}),
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.wbd_cyc_slave (),
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.wbd_err_slave (),
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.wbd_rty_slave ()
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);
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//-------------------------------------------
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// GMAC core instantiation
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//-------------------------------------------
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g_mac_top u_eth_dut (
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.scan_mode (1'b0 ),
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.s_reset_n (gen_resetn ),
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.tx_reset_n (gen_resetn ),
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.rx_reset_n (gen_resetn ),
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.reset_mdio_clk_n (gen_resetn ),
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.app_reset_n (gen_resetn ),
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// Reg Bus Interface Signal
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. reg_cs (reg_mac_cs ),
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. reg_wr (reg_mac_wr ),
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. reg_addr (reg_mac_addr[5:2] ),
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. reg_wdata (reg_mac_wdata ),
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. reg_be (reg_mac_be ),
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// Outputs
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. reg_rdata (reg_mac_rdata ),
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. reg_ack (reg_mac_ack ),
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.app_clk (app_clk ),
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// Application RX FIFO Interface
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.app_txfifo_wren_i (app_txfifo_wren_i ),
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.app_txfifo_wrdata_i (app_txfifo_wrdata_i ),
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.app_txfifo_addr (app_txfifo_addr ),
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.app_txfifo_full_o (app_txfifo_full_o ),
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.app_txfifo_afull_o (app_txfifo_afull_o ),
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.app_txfifo_space_o ( ),
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// Application TX FIFO Interface
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.app_rxfifo_rden_i (app_rxfifo_rden_i ),
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.app_rxfifo_empty_o (app_rxfifo_empty_o ),
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.app_rxfifo_aempty_o (app_rxfifo_aempty_o ),
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.app_rxfifo_cnt_o ( ),
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.app_rxfifo_rdata_o (app_rxfifo_rddata_o ),
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.app_rxfifo_addr (app_rxfifo_addr ),
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.app_rx_desc_req (app_rx_desc_req ),
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.app_rx_desc_ack (app_rx_desc_ack ),
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.app_rx_desc_discard (app_rx_desc_discard ),
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.app_rx_desc_data (app_rx_desc_data ),
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// Line Side Interface TX Path
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.phy_tx_en (phy_tx_en ),
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.phy_tx_er ( ),
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.phy_txd (phy_txd ),
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.phy_tx_clk (phy_tx_clk ),
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// Line Side Interface RX Path
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.phy_rx_clk (phy_rx_clk ),
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.phy_rx_er (1'b0 ),
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.phy_rx_dv (phy_rx_dv ),
|
|
.phy_rxd (phy_rxd ),
|
|
.phy_crs (1'b0 ),
|
|
|
|
//MDIO interface
|
|
.mdio_clk (mdio_clk ),
|
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.mdio_in (mdio_in ),
|
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.mdio_out_en (mdio_out_en ),
|
|
.mdio_out (mdio_out ),
|
|
|
|
// QCounter
|
|
.rx_buf_qbase_addr (cfg_rx_buf_qbase_addr),
|
|
.tx_buf_qbase_addr (cfg_tx_buf_qbase_addr),
|
|
|
|
.tx_qcnt_inc (tx_qcnt_inc),
|
|
.tx_qcnt_dec (tx_qcnt_dec),
|
|
.rx_qcnt_inc (rx_qcnt_inc),
|
|
.rx_qcnt_dec (rx_qcnt_dec),
|
|
.tx_qcnt (tx_qcnt),
|
|
.rx_qcnt (rx_qcnt)
|
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
|
|
wb_rd_mem2mem #(32,4,13,4) u_wb_gmac_tx (
|
|
|
|
.rst_n ( gen_resetn ),
|
|
.clk ( app_clk ),
|
|
|
|
// descriptor handshake
|
|
.cfg_desc_baddr (cfg_tx_buf_qbase_addr),
|
|
.desc_q_empty (tx_q_empty ),
|
|
|
|
// Master Interface Signal
|
|
.mem_taddr ( 4'h1 ),
|
|
.mem_full (app_txfifo_full_o ),
|
|
.mem_afull (app_txfifo_afull_o ),
|
|
.mem_wr (app_txfifo_wren_i ),
|
|
.mem_din (app_txfifo_wrdata_i ),
|
|
|
|
// Slave Interface Signal
|
|
.wbo_dout ( wbgt_dout ),
|
|
.wbo_taddr ( wbgt_taddr ),
|
|
.wbo_addr ( wbgt_addr ),
|
|
.wbo_be ( wbgt_be ),
|
|
.wbo_we ( wbgt_we ),
|
|
.wbo_ack ( wbgt_ack ),
|
|
.wbo_stb ( wbgt_stb ),
|
|
.wbo_cyc ( wbgt_cyc ),
|
|
.wbo_err ( wbgt_err ),
|
|
.wbo_rty ( wbgt_rty )
|
|
);
|
|
|
|
|
|
wb_wr_mem2mem #(32,4,13,4) u_wb_gmac_rx(
|
|
|
|
.rst_n ( gen_resetn ),
|
|
.clk ( app_clk ),
|
|
|
|
|
|
// Master Interface Signal
|
|
.mem_taddr ( 4'h1 ),
|
|
.mem_addr (app_rxfifo_addr ),
|
|
.mem_empty (app_rxfifo_empty_o ),
|
|
.mem_aempty (app_rxfifo_aempty_o ),
|
|
.mem_rd (app_rxfifo_rden_i ),
|
|
.mem_dout (app_rxfifo_rddata_o[7:0]),
|
|
.mem_eop (app_rxfifo_rddata_o[8]),
|
|
|
|
.cfg_desc_baddr (cfg_rx_buf_qbase_addr ),
|
|
.desc_req (app_rx_desc_req ),
|
|
.desc_ack (app_rx_desc_ack ),
|
|
.desc_disccard (app_rx_desc_discard ),
|
|
.desc_data (app_rx_desc_data ),
|
|
// Slave Interface Signal
|
|
.wbo_din ( wbgr_din ),
|
|
.wbo_taddr ( wbgr_taddr ),
|
|
.wbo_addr ( wbgr_addr ),
|
|
.wbo_be ( wbgr_be ),
|
|
.wbo_we ( wbgr_we ),
|
|
.wbo_ack ( wbgr_ack ),
|
|
.wbo_stb ( wbgr_stb ),
|
|
.wbo_cyc ( wbgr_cyc ),
|
|
.wbo_err ( wbgr_err ),
|
|
.wbo_rty ( wbgr_rty )
|
|
);
|
|
|
|
//-------------------------------------
|
|
// UART core instantiation
|
|
//-------------------------------------
|
|
|
|
uart_core u_uart_core
|
|
|
|
(
|
|
. line_reset_n (gen_resetn ),
|
|
. line_clk_16x (uart_clk_16x ),
|
|
|
|
. app_reset_n (gen_resetn ),
|
|
. app_clk (app_clk ),
|
|
|
|
|
|
// Reg Bus Interface Signal
|
|
. reg_cs (reg_uart_cs ),
|
|
. reg_wr (reg_uart_wr ),
|
|
. reg_addr (reg_uart_addr[5:2] ),
|
|
. reg_wdata (reg_uart_wdata ),
|
|
. reg_be (reg_uart_be ),
|
|
|
|
// Outputs
|
|
. reg_rdata (reg_uart_rdata ),
|
|
. reg_ack (reg_uart_ack ),
|
|
|
|
|
|
|
|
// Line Interface
|
|
. si (si ),
|
|
. so (so )
|
|
|
|
);
|
|
|
|
|
|
//--------------------------------
|
|
// SPI core instantiation
|
|
//--------------------------------
|
|
|
|
|
|
spi_core u_spi_core (
|
|
|
|
. clk (app_clk ),
|
|
. reset_n (gen_resetn ),
|
|
|
|
// Reg Bus Interface Signal
|
|
. reg_cs (reg_spi_cs ),
|
|
. reg_wr (reg_spi_wr ),
|
|
. reg_addr (reg_spi_addr[5:2] ),
|
|
. reg_wdata (reg_spi_wdata ),
|
|
. reg_be (reg_spi_be ),
|
|
|
|
// Outputs
|
|
. reg_rdata (reg_spi_rdata ),
|
|
. reg_ack (reg_spi_ack ),
|
|
|
|
|
|
. sck (spi_sck ),
|
|
. so (spi_so ),
|
|
. si (spi_si ),
|
|
. cs_n (spi_cs_n )
|
|
|
|
);
|
|
|
|
|
|
|
|
oc8051_top u_8051_core (
|
|
. wb_rst_i (risc_reset ),
|
|
. wb_clk_i (app_clk ),
|
|
|
|
//interface to instruction rom
|
|
. wbi_adr_o (wbi_risc_adr ),
|
|
. wbi_dat_i (wbi_risc_rdata ),
|
|
. wbi_stb_o (wbi_risc_stb ),
|
|
. wbi_ack_i (wbi_risc_ack ),
|
|
. wbi_cyc_o (wbi_risc_cyc ),
|
|
. wbi_err_i (wbi_risc_err ),
|
|
|
|
//interface to data ram
|
|
. wbd_dat_i (wbd_risc_rdata ),
|
|
. wbd_dat_o (wbd_risc_wdata ),
|
|
. wbd_adr_o (wbd_risc_adr ),
|
|
. wbd_we_o (wbd_risc_we ),
|
|
. wbd_ack_i (wbd_risc_ack ),
|
|
. wbd_stb_o (wbd_risc_stb ),
|
|
. wbd_cyc_o (wbd_risc_cyc ),
|
|
. wbd_err_i (wbd_risc_err ),
|
|
|
|
// interrupt interface
|
|
. int0_i ( ),
|
|
. int1_i ( ),
|
|
|
|
|
|
// port interface
|
|
`ifdef OC8051_PORTS
|
|
`ifdef OC8051_PORT0
|
|
.p0_i ( p0 ),
|
|
.p0_o ( p0 ),
|
|
`endif
|
|
|
|
`ifdef OC8051_PORT1
|
|
.p1_i ( p1 ),
|
|
.p1_o ( p1 ),
|
|
`endif
|
|
|
|
`ifdef OC8051_PORT2
|
|
.p2_i ( p2 ),
|
|
.p2_o ( p2 ),
|
|
`endif
|
|
|
|
`ifdef OC8051_PORT3
|
|
.p3_i ( p3 ),
|
|
.p3_o ( p3 ),
|
|
`endif
|
|
`endif
|
|
|
|
// serial interface
|
|
`ifdef OC8051_UART
|
|
.rxd_i ( ),
|
|
.txd_o ( ),
|
|
`endif
|
|
|
|
// counter interface
|
|
`ifdef OC8051_TC01
|
|
.t0_i ( ),
|
|
.t1_i ( ),
|
|
`endif
|
|
|
|
`ifdef OC8051_TC2
|
|
.t2_i ( ),
|
|
.t2ex_i ( ),
|
|
`endif
|
|
|
|
// BIST
|
|
`ifdef OC8051_BIST
|
|
.scanb_rst ( ),
|
|
.scanb_clk ( ),
|
|
.scanb_si ( ),
|
|
.scanb_so ( ),
|
|
.scanb_en ( ),
|
|
`endif
|
|
// external access (active low)
|
|
.ea_in (ea_in )
|
|
);
|
|
|
|
endmodule
|
|
|
No newline at end of file
|
No newline at end of file
|
