| Line 83... |
Line 83... |
cf_mac_mode,
|
cf_mac_mode,
|
cf_chk_rx_dfl,
|
cf_chk_rx_dfl,
|
cf2mi_rmii_en,
|
cf2mi_rmii_en,
|
|
|
cfg_uni_mac_mode_change_i,
|
cfg_uni_mac_mode_change_i,
|
cfg_crs_flow_ctrl_enb_i,
|
|
|
|
//CHANNEL enable
|
//CHANNEL enable
|
cf2tx_ch_en,
|
cf2tx_ch_en,
|
//CHANNEL CONTROL TX
|
//CHANNEL CONTROL TX
|
cf_silent_mode,
|
cf_silent_mode,
|
| Line 97... |
Line 96... |
cf2tx_append_fcs,
|
cf2tx_append_fcs,
|
//CHANNEL CONTROL RX
|
//CHANNEL CONTROL RX
|
cf2rx_ch_en,
|
cf2rx_ch_en,
|
cf2rx_strp_pad_en,
|
cf2rx_strp_pad_en,
|
cf2rx_snd_crc,
|
cf2rx_snd_crc,
|
cf2rx_pause_en,
|
|
cf2rx_addrchk_en,
|
|
cf2rx_runt_pkt_en,
|
cf2rx_runt_pkt_en,
|
cf2af_broadcast_disable,
|
|
cf_mac_sa,
|
cf_mac_sa,
|
cfg_ip_sa,
|
cfg_ip_sa,
|
cfg_mac_filter,
|
cfg_mac_filter,
|
|
|
cf2tx_pause_quanta,
|
|
cf2rx_max_pkt_sz,
|
cf2rx_max_pkt_sz,
|
cf2tx_force_bad_fcs,
|
cf2tx_force_bad_fcs,
|
cf2tx_tstate_mode,
|
|
//MDIO CONTROL & DATA
|
//MDIO CONTROL & DATA
|
cf2md_datain,
|
cf2md_datain,
|
cf2md_regad,
|
cf2md_regad,
|
cf2md_phyad,
|
cf2md_phyad,
|
cf2md_op,
|
cf2md_op,
|
| Line 141... |
Line 135... |
input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
|
input tx_sts_vld ; // tx status valid indication, sync w.r.t app clk
|
input tx_sts ; // tx status bits
|
input tx_sts ; // tx status bits
|
|
|
//List of Inputs
|
//List of Inputs
|
|
|
input app_clk, app_reset_n;
|
input app_clk ;
|
|
input app_reset_n ;
|
input md2cf_cmd_done; // Read/Write MDIO completed
|
input md2cf_cmd_done; // Read/Write MDIO completed
|
input md2cf_status; // MDIO transfer error
|
input md2cf_status; // MDIO transfer error
|
input [15:0] md2cf_data; // Data from PHY for a
|
input [15:0] md2cf_data; // Data from PHY for a
|
// mdio read access
|
// mdio read access
|
|
|
| Line 155... |
Line 150... |
output cf_mac_mode; // mac mode set this to 1 for 100Mbs/10Mbs
|
output cf_mac_mode; // mac mode set this to 1 for 100Mbs/10Mbs
|
output cf_chk_rx_dfl; // Check for RX Deferal
|
output cf_chk_rx_dfl; // Check for RX Deferal
|
output [47:0] cf_mac_sa;
|
output [47:0] cf_mac_sa;
|
output [31:0] cfg_ip_sa;
|
output [31:0] cfg_ip_sa;
|
output [31:0] cfg_mac_filter;
|
output [31:0] cfg_mac_filter;
|
output [15:0] cf2tx_pause_quanta;
|
|
output cf2tx_ch_en; //enable the TX channel
|
output cf2tx_ch_en; //enable the TX channel
|
output cf_silent_mode; // PHY Inactive
|
output cf_silent_mode; // PHY Inactive
|
output [7:0] cf2df_dfl_single; //number of clk ticks for dfl
|
output [7:0] cf2df_dfl_single; //number of clk ticks for dfl
|
output [7:0] cf2df_dfl_single_rx; //number of clk ticks for dfl
|
output [7:0] cf2df_dfl_single_rx; //number of clk ticks for dfl
|
|
|
output cf2tx_tstate_mode; //used for OFN's tstate enable on authentication interface
|
|
output cf2tx_pad_enable; //enable padding, < 64 bytes
|
output cf2tx_pad_enable; //enable padding, < 64 bytes
|
output cf2tx_append_fcs; //append CRC for TX frames
|
output cf2tx_append_fcs; //append CRC for TX frames
|
output cf2rx_ch_en; //Enable RX channel
|
output cf2rx_ch_en; //Enable RX channel
|
output cf2rx_strp_pad_en; //strip the padded bytes on RX frame
|
output cf2rx_strp_pad_en; //strip the padded bytes on RX frame
|
output cf2rx_snd_crc; //send FCS to application, else strip
|
output cf2rx_snd_crc; //send FCS to application, else strip
|
//the FCS before sending to application
|
//the FCS before sending to application
|
output cf2rx_pause_en; //enable flow control for full duplex using
|
|
//pause control frames
|
|
output cf2mi_loopback_en; // TX to RX loop back enable
|
output cf2mi_loopback_en; // TX to RX loop back enable
|
output cf2rx_addrchk_en; //check the destination address, filter
|
|
output cf2rx_runt_pkt_en; //don't throw packets less than 64 bytes
|
output cf2rx_runt_pkt_en; //don't throw packets less than 64 bytes
|
output cf2af_broadcast_disable;
|
|
output [15:0] cf2md_datain;
|
output [15:0] cf2md_datain;
|
output [4:0] cf2md_regad;
|
output [4:0] cf2md_regad;
|
output [4:0] cf2md_phyad;
|
output [4:0] cf2md_phyad;
|
output cf2md_op;
|
output cf2md_op;
|
output cf2md_go;
|
output cf2md_go;
|
|
|
output [15:0] cf2rx_max_pkt_sz; //max rx packet size
|
output [15:0] cf2rx_max_pkt_sz; //max rx packet size
|
output cf2tx_force_bad_fcs; //force bad fcs on tx
|
output cf2tx_force_bad_fcs; //force bad fcs on tx
|
|
|
output cfg_uni_mac_mode_change_i;
|
output cfg_uni_mac_mode_change_i;
|
output cfg_crs_flow_ctrl_enb_i;
|
|
|
|
|
|
// Wire assignments for output signals
|
// Wire assignments for output signals
|
wire [15:0] cf2md_datain;
|
wire [15:0] cf2md_datain;
|
wire [4:0] cf2md_regad;
|
wire [4:0] cf2md_regad;
|
| Line 229... |
Line 217... |
wire [7:0] mac_sa_out_2;
|
wire [7:0] mac_sa_out_2;
|
wire [7:0] mac_sa_out_3;
|
wire [7:0] mac_sa_out_3;
|
wire [7:0] mac_sa_out_4;
|
wire [7:0] mac_sa_out_4;
|
wire [7:0] mac_sa_out_5;
|
wire [7:0] mac_sa_out_5;
|
wire [7:0] mac_sa_out_6;
|
wire [7:0] mac_sa_out_6;
|
wire [7:0] pause_quanta_out_1;
|
|
wire [7:0] pause_quanta_out_2;
|
|
wire [47:0] cf_mac_sa;
|
wire [47:0] cf_mac_sa;
|
wire [15:0] cf2tx_pause_quanta;
|
|
wire [15:0] cf2rx_max_pkt_sz;
|
wire [15:0] cf2rx_max_pkt_sz;
|
wire cf2tx_force_bad_fcs;
|
wire cf2tx_force_bad_fcs;
|
wire cf2tx_tstate_mode;
|
|
reg force_bad_fcs;
|
reg force_bad_fcs;
|
reg cont_force_bad_fcs;
|
reg cont_force_bad_fcs;
|
wire [31:0] mdio_stat_out;
|
wire [31:0] mdio_stat_out;
|
reg cf2tx_force_bad_fcs_en;
|
reg cf2tx_force_bad_fcs_en;
|
reg cf2tx_cont_force_bad_fcs_en;
|
reg cf2tx_cont_force_bad_fcs_en;
|
| Line 409... |
Line 393... |
);
|
);
|
|
|
assign cf2tx_ch_en = tx_cntrl_out_1[0];
|
assign cf2tx_ch_en = tx_cntrl_out_1[0];
|
assign cf2tx_pad_enable = tx_cntrl_out_1[3];
|
assign cf2tx_pad_enable = tx_cntrl_out_1[3];
|
assign cf2tx_append_fcs = tx_cntrl_out_1[4];
|
assign cf2tx_append_fcs = tx_cntrl_out_1[4];
|
assign cf2tx_tstate_mode = tx_cntrl_out_1[6];
|
|
assign cf2tx_force_bad_fcs = tx_cntrl_out_1[7];
|
assign cf2tx_force_bad_fcs = tx_cntrl_out_1[7];
|
|
|
assign reg_0[15:0] = {tx_cntrl_out_2,tx_cntrl_out_1};
|
assign reg_0[15:0] = {tx_cntrl_out_2,tx_cntrl_out_1};
|
|
|
//=========================================================================//
|
//=========================================================================//
|
// RX_CNTRL_REGISTER 1 : Address Value 04H
|
// RX_CNTRL_REGISTER 1 : Address Value 04H
|
// BIT[0] = Receive Channel Enable
|
// BIT[0] = Receive Channel Enable
|
// BIT[1] = Strip Padding from the Receive data
|
// BIT[1] = Strip Padding from the Receive data
|
// BIT[2] = Send CRC along with data to the host
|
// BIT[2] = Send CRC along with data to the host
|
// BIT[3] = Enable pause frame detect
|
|
// BIT[4] = Check RX Deferral
|
// BIT[4] = Check RX Deferral
|
// BIT[5] = Receive Address Check Enable
|
// BIT[5] = Receive Address Check Enable
|
// BIT[6] = Receive Runt Packet
|
// BIT[6] = Receive Runt Packet
|
// BIT[7] = Broad Cast Rx Disable
|
// BIT[7] = Broad Cast Rx Disable
|
// BIT[31:8] = Reserved
|
// BIT[31:8] = Reserved
|
| Line 439... |
Line 421... |
);
|
);
|
|
|
assign cf2rx_ch_en = rx_cntrl_out_1[0];
|
assign cf2rx_ch_en = rx_cntrl_out_1[0];
|
assign cf2rx_strp_pad_en = rx_cntrl_out_1[1];
|
assign cf2rx_strp_pad_en = rx_cntrl_out_1[1];
|
assign cf2rx_snd_crc = rx_cntrl_out_1[2];
|
assign cf2rx_snd_crc = rx_cntrl_out_1[2];
|
assign cf2rx_pause_en = rx_cntrl_out_1[3];
|
|
assign cf_chk_rx_dfl = rx_cntrl_out_1[4];
|
assign cf_chk_rx_dfl = rx_cntrl_out_1[4];
|
assign cf2rx_addrchk_en = rx_cntrl_out_1[5];
|
|
assign cf2rx_runt_pkt_en = rx_cntrl_out_1[6];
|
assign cf2rx_runt_pkt_en = rx_cntrl_out_1[6];
|
assign cf2af_broadcast_disable = rx_cntrl_out_1[7];
|
|
|
|
|
|
assign reg_1[7:0] = {rx_cntrl_out_1};
|
assign reg_1[7:0] = {rx_cntrl_out_1};
|
//========================================================================//
|
//========================================================================//
|
//TRANSMIT DEFFERAL CONTROL REGISTER: Address value 08H
|
//TRANSMIT DEFFERAL CONTROL REGISTER: Address value 08H
|
| Line 504... |
Line 483... |
|
|
assign cf_mac_mode = mac_mode_out[0];
|
assign cf_mac_mode = mac_mode_out[0];
|
assign cf2mi_rmii_en = mac_mode_out[1];
|
assign cf2mi_rmii_en = mac_mode_out[1];
|
assign cf2mi_loopback_en = mac_mode_out[2];
|
assign cf2mi_loopback_en = mac_mode_out[2];
|
assign cf_silent_mode = mac_mode_out[5];
|
assign cf_silent_mode = mac_mode_out[5];
|
assign cfg_crs_flow_ctrl_enb_i = mac_mode_out[6];
|
|
assign cfg_uni_mac_mode_change_i = mac_mode_out[7];
|
assign cfg_uni_mac_mode_change_i = mac_mode_out[7];
|
|
|
|
|
assign reg_3[7:0] = {mac_mode_out};
|
assign reg_3[7:0] = {mac_mode_out};
|
//========================================================================//
|
//========================================================================//
|
| Line 710... |
Line 688... |
//List of Outs
|
//List of Outs
|
.data_out (cf2rx_max_pkt_sz[15:8] )
|
.data_out (cf2rx_max_pkt_sz[15:8] )
|
);
|
);
|
|
|
assign reg_8[15:0] = cf2rx_max_pkt_sz[15:0];
|
assign reg_8[15:0] = cf2rx_max_pkt_sz[15:0];
|
//========================================================================//
|
|
//Pause Quanta Register 24
|
|
|
|
generic_register #(8,0 ) pause_quanta_reg_1 (
|
|
.we ({8{sw_wr_en_9 & wr_be[0] }}),
|
|
.data_in (reg_wdata[7:0] ),
|
|
.reset_n (app_reset_n ),
|
|
.clk (app_clk ),
|
|
|
|
//List of Outs
|
|
.data_out (pause_quanta_out_1[7:0] )
|
|
);
|
|
|
|
generic_register #(8,0 ) pause_quanta_reg_2 (
|
|
.we ({8{sw_wr_en_9 & wr_be[1] }}),
|
|
.data_in (reg_wdata[15:8] ),
|
|
.reset_n (app_reset_n ),
|
|
.clk (app_clk ),
|
|
|
|
//List of Outs
|
|
.data_out (pause_quanta_out_2[7:0] )
|
|
);
|
|
|
|
|
|
assign cf2tx_pause_quanta = {pause_quanta_out_1 , pause_quanta_out_2};
|
|
|
|
|
|
assign reg_9[15:0] = cf2tx_pause_quanta;
|
|
|
|
|
assign reg_9 = 0; // free
|
|
|
|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// RX-Clock Static Counter Status Signal
|
// RX-Clock Static Counter Status Signal
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
