| Line 108... |
Line 108... |
//MDIO CONTROL & DATA
|
//MDIO CONTROL & DATA
|
cf2md_datain,
|
cf2md_datain,
|
cf2md_regad,
|
cf2md_regad,
|
cf2md_phyad,
|
cf2md_phyad,
|
cf2md_op,
|
cf2md_op,
|
cf2md_go);
|
cf2md_go,
|
|
|
|
rx_buf_base_addr,
|
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tx_buf_base_addr,
|
|
rx_buf_qbase_addr,
|
|
tx_buf_qbase_addr,
|
|
|
|
tx_qcnt_inc,
|
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tx_qcnt_dec,
|
|
tx_qcnt,
|
|
|
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rx_qcnt_inc,
|
|
rx_qcnt_dec,
|
|
rx_qcnt
|
|
|
|
);
|
|
|
parameter mac_mdio_en = 1'b1;
|
parameter mac_mdio_en = 1'b1;
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|
|
|
|
//pin out definations
|
//pin out definations
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| Line 174... |
Line 189... |
output [15:0] cf2rx_max_pkt_sz; //max rx packet size
|
output [15:0] cf2rx_max_pkt_sz; //max rx packet size
|
output cf2tx_force_bad_fcs; //force bad fcs on tx
|
output cf2tx_force_bad_fcs; //force bad fcs on tx
|
|
|
output cfg_uni_mac_mode_change_i;
|
output cfg_uni_mac_mode_change_i;
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|
|
|
output [3:0] rx_buf_base_addr; // Rx Data Buffer Base Address
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output [3:0] tx_buf_base_addr; // Tx Data Buffer Base Address
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output [9:0] rx_buf_qbase_addr; // Rx Q Base Address
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output [9:0] tx_buf_qbase_addr; // Tx Q Base Address
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|
|
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input tx_qcnt_inc;
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input tx_qcnt_dec;
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output [3:0] tx_qcnt;
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|
|
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input rx_qcnt_inc;
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input rx_qcnt_dec;
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output [3:0] rx_qcnt;
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|
|
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|
// Wire assignments for output signals
|
// Wire assignments for output signals
|
wire [15:0] cf2md_datain;
|
wire [15:0] cf2md_datain;
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wire [4:0] cf2md_regad;
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wire [4:0] cf2md_regad;
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wire [4:0] cf2md_phyad;
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wire [4:0] cf2md_phyad;
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| Line 196... |
Line 224... |
|
|
|
|
// Wire and Reg assignments for local signals
|
// Wire and Reg assignments for local signals
|
reg int_md2cf_status;
|
reg int_md2cf_status;
|
wire [7:0] mac_mode_out;
|
wire [7:0] mac_mode_out;
|
wire [7:0] tx_cntrl_out_1, rx_cntrl_out_1;
|
wire [7:0] mac_cntrl_out_1, mac_cntrl_out_2;
|
wire [7:0] tx_cntrl_out_2, rx_cntrl_out_2;
|
|
wire [7:0] dfl_params_rx_out;
|
wire [7:0] dfl_params_rx_out;
|
wire [7:0] dfl_params1_out;
|
wire [7:0] dfl_params1_out;
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wire [7:0] slottime_out_1;
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wire [7:0] slottime_out_1;
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wire [7:0] slottime_out_2;
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wire [7:0] slottime_out_2;
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wire [31:0] mdio_cmd_out;
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wire [31:0] mdio_cmd_out;
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| Line 368... |
Line 395... |
// BIT[5] = Perform a Two Part Deferral
|
// BIT[5] = Perform a Two Part Deferral
|
// BIT[6] = RMII Enable bit
|
// BIT[6] = RMII Enable bit
|
// BIT[7] = Force TX FCS Error
|
// BIT[7] = Force TX FCS Error
|
|
|
|
|
generic_register #(8,0 ) tx_cntrl_reg_1 (
|
generic_register #(8,0 ) u_mac_cntrl_reg_1 (
|
.we ({8{sw_wr_en_0 &
|
.we ({8{sw_wr_en_0 &
|
wr_be[0] }} ),
|
wr_be[0] }} ),
|
.data_in (reg_wdata[7:0] ),
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.data_in (reg_wdata[7:0] ),
|
.reset_n (app_reset_n ),
|
.reset_n (app_reset_n ),
|
.clk (app_clk ),
|
.clk (app_clk ),
|
|
|
//List of Outs
|
//List of Outs
|
.data_out (tx_cntrl_out_1[7:0] )
|
.data_out (mac_cntrl_out_1[7:0] )
|
);
|
);
|
|
|
generic_register #(8,0 ) tx_cntrl_reg_2 (
|
generic_register #(8,0 ) u_mac_cntrl_reg_2 (
|
.we ({8{sw_wr_en_0 &
|
.we ({8{sw_wr_en_0 &
|
wr_be[1] }} ),
|
wr_be[1] }} ),
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.data_in (reg_wdata[15:8] ),
|
.data_in (reg_wdata[15:8] ),
|
.reset_n (app_reset_n ),
|
.reset_n (app_reset_n ),
|
.clk (app_clk ),
|
.clk (app_clk ),
|
|
|
//List of Outs
|
//List of Outs
|
.data_out (tx_cntrl_out_2[7:0] )
|
.data_out (mac_cntrl_out_2[7:0] )
|
|
);
|
|
|
|
generic_register #(8,0 ) u_mac_cntrl_reg_3 (
|
|
.we ({8{sw_wr_en_0 & wr_be[2] }}),
|
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.data_in (reg_wdata[3:0] ),
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|
.reset_n (app_reset_n ),
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|
.clk (app_clk ),
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|
|
|
//List of Outs
|
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.data_out ({tx_buf_base_addr[3:0],
|
|
rx_buf_base_addr[3:0]} )
|
);
|
);
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|
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assign cf2tx_ch_en = tx_cntrl_out_1[0];
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|
assign cf2tx_pad_enable = tx_cntrl_out_1[3];
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assign cf2tx_append_fcs = tx_cntrl_out_1[4];
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assign cf2tx_force_bad_fcs = tx_cntrl_out_1[7];
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|
|
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assign reg_0[15:0] = {tx_cntrl_out_2,tx_cntrl_out_1};
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// TX Control Register
|
|
assign cf2tx_ch_en = mac_cntrl_out_1[0];
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|
assign cf2tx_pad_enable = mac_cntrl_out_1[3];
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|
assign cf2tx_append_fcs = mac_cntrl_out_1[4];
|
|
assign cf2tx_force_bad_fcs = mac_cntrl_out_1[7];
|
|
|
//=========================================================================//
|
// RX_CNTRL_REGISTER
|
// RX_CNTRL_REGISTER 1 : Address Value 04H
|
|
// BIT[0] = Receive Channel Enable
|
// BIT[0] = Receive Channel Enable
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// BIT[1] = Strip Padding from the Receive data
|
// BIT[1] = Strip Padding from the Receive data
|
// BIT[2] = Send CRC along with data to the host
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// BIT[2] = Send CRC along with data to the host
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// BIT[4] = Check RX Deferral
|
// BIT[4] = Check RX Deferral
|
// BIT[5] = Receive Address Check Enable
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|
// BIT[6] = Receive Runt Packet
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// BIT[6] = Receive Runt Packet
|
// BIT[7] = Broad Cast Rx Disable
|
assign cf2rx_ch_en = mac_cntrl_out_2[0];
|
// BIT[31:8] = Reserved
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assign cf2rx_strp_pad_en = mac_cntrl_out_2[1];
|
generic_register #(8,0 ) rx_cntrl_reg_1 (
|
assign cf2rx_snd_crc = mac_cntrl_out_2[2];
|
.we ({8{sw_wr_en_1 &
|
assign cf_chk_rx_dfl = mac_cntrl_out_2[4];
|
wr_be[0] }} ),
|
assign cf2rx_runt_pkt_en = mac_cntrl_out_2[6];
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.data_in (reg_wdata[7:0] ),
|
|
.reset_n (app_reset_n ),
|
assign reg_0[23:0] = {tx_buf_base_addr[3:0],
|
.clk (app_clk ),
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rx_buf_base_addr[3:0],
|
|
mac_cntrl_out_2[7:0],
|
//List of Outs
|
mac_cntrl_out_1[7:0]};
|
.data_out (rx_cntrl_out_1[7:0] )
|
|
);
|
|
|
|
assign cf2rx_ch_en = rx_cntrl_out_1[0];
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|
assign cf2rx_strp_pad_en = rx_cntrl_out_1[1];
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|
assign cf2rx_snd_crc = rx_cntrl_out_1[2];
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|
assign cf_chk_rx_dfl = rx_cntrl_out_1[4];
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|
assign cf2rx_runt_pkt_en = rx_cntrl_out_1[6];
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|
|
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|
|
assign reg_1[7:0] = {rx_cntrl_out_1};
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// reg1 free
|
//========================================================================//
|
//========================================================================//
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//TRANSMIT DEFFERAL CONTROL REGISTER: Address value 08H
|
//TRANSMIT DEFFERAL CONTROL REGISTER: Address value 08H
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//BIT[7:0] = Defferal TX
|
//BIT[7:0] = Defferal TX
|
//BIT[15:8] = Defferal RX
|
//BIT[15:8] = Defferal RX
|
|
|
| Line 690... |
Line 718... |
);
|
);
|
|
|
assign reg_8[15:0] = cf2rx_max_pkt_sz[15:0];
|
assign reg_8[15:0] = cf2rx_max_pkt_sz[15:0];
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|
|
|
|
assign reg_9 = 0; // free
|
//========================================================================//
|
|
//MAC max packet size Register 20
|
|
|
|
generic_register #(2,0 ) m_rx_qbase_addr_1 (
|
|
.we ({8{sw_wr_en_9 & wr_be[0] }}),
|
|
.data_in (reg_wdata[7:6] ),
|
|
.reset_n (app_reset_n ),
|
|
.clk (app_clk ),
|
|
|
|
//List of Outs
|
|
.data_out (rx_buf_qbase_addr[1:0] )
|
|
);
|
|
|
|
generic_register #(8,0 ) m_rx_qbase_addr_2 (
|
|
.we ({8{sw_wr_en_9 & wr_be[1] }}),
|
|
.data_in (reg_wdata[15:8] ),
|
|
.reset_n (app_reset_n ),
|
|
.clk (app_clk ),
|
|
|
|
//List of Outs
|
|
.data_out (rx_buf_qbase_addr[9:2] )
|
|
);
|
|
|
|
|
|
generic_register #(2,0 ) m_tx_qbase_addr_1 (
|
|
.we ({8{sw_wr_en_9 & wr_be[2] }}),
|
|
.data_in (reg_wdata[23:22] ),
|
|
.reset_n (app_reset_n ),
|
|
.clk (app_clk ),
|
|
|
|
//List of Outs
|
|
.data_out (tx_buf_qbase_addr[1:0] )
|
|
);
|
|
|
|
generic_register #(8,0 ) m_tx_qbase_addr_2 (
|
|
.we ({8{sw_wr_en_9 & wr_be[3] }}),
|
|
.data_in (reg_wdata[31:24] ),
|
|
.reset_n (app_reset_n ),
|
|
.clk (app_clk ),
|
|
|
|
//List of Outs
|
|
.data_out (tx_buf_qbase_addr[9:2] )
|
|
);
|
|
|
|
|
|
assign reg_9[15:0] = {rx_buf_qbase_addr[9:0],6'h0};
|
|
assign reg_9[31:16] = {tx_buf_qbase_addr[9:0],6'h0};
|
|
|
|
|
|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// RX-Clock Static Counter Status Signal
|
// RX-Clock Static Counter Status Signal
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
| Line 707... |
Line 782... |
stat_counter #(16) u_stat_rx_good_frm (
|
stat_counter #(16) u_stat_rx_good_frm (
|
// Clock and Reset Signals
|
// Clock and Reset Signals
|
. sys_clk (app_clk ),
|
. sys_clk (app_clk ),
|
. s_reset_n (app_reset_n ),
|
. s_reset_n (app_reset_n ),
|
|
|
. count_trigger (rx_good_frm_trig),
|
. count_inc (rx_good_frm_trig),
|
|
. count_dec (1'b0 ),
|
|
|
. reg_sel (sw_wr_en_10 ),
|
. reg_sel (sw_wr_en_10 ),
|
. reg_wr_data (reg_wdata[15:0] ),
|
. reg_wr_data (reg_wdata[15:0] ),
|
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
|
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
|
|
|
| Line 722... |
Line 798... |
stat_counter #(16) u_stat_rx_bad_frm (
|
stat_counter #(16) u_stat_rx_bad_frm (
|
// Clock and Reset Signals
|
// Clock and Reset Signals
|
. sys_clk (app_clk ),
|
. sys_clk (app_clk ),
|
. s_reset_n (app_reset_n ),
|
. s_reset_n (app_reset_n ),
|
|
|
. count_trigger (rx_bad_frm_trig ),
|
. count_inc (rx_bad_frm_trig ),
|
|
. count_dec (1'b0 ),
|
|
|
. reg_sel (sw_wr_en_11 ),
|
. reg_sel (sw_wr_en_10 ),
|
. reg_wr_data (reg_wdata[15:0] ),
|
. reg_wr_data (reg_wdata[31:16] ),
|
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
|
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
|
|
|
. cntr_intr ( ),
|
. cntr_intr ( ),
|
. cntrout (reg_11[15:0] )
|
. cntrout (reg_10[31:16] )
|
);
|
);
|
|
|
|
|
wire tx_good_frm_trig = tx_sts_vld ;
|
wire tx_good_frm_trig = tx_sts_vld ;
|
|
|
stat_counter #(16) u_stat_tx_good_frm (
|
stat_counter #(16) u_stat_tx_good_frm (
|
// Clock and Reset Signals
|
// Clock and Reset Signals
|
. sys_clk (app_clk ),
|
. sys_clk (app_clk ),
|
. s_reset_n (app_reset_n ),
|
. s_reset_n (app_reset_n ),
|
|
|
. count_trigger (tx_good_frm_trig ),
|
. count_inc (tx_good_frm_trig ),
|
|
. count_dec (1'b0 ),
|
|
|
. reg_sel (sw_wr_en_12 ),
|
. reg_sel (sw_wr_en_11 ),
|
. reg_wr_data (reg_wdata[15:0] ),
|
. reg_wr_data (reg_wdata[15:0] ),
|
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
|
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
|
|
|
. cntr_intr ( ),
|
. cntr_intr ( ),
|
. cntrout (reg_12[15:0] )
|
. cntrout (reg_11[15:0] )
|
|
);
|
|
|
|
// reg_12 & reg_13 is free
|
|
|
|
stat_counter #(4) u_rx_qcnt (
|
|
// Clock and Reset Signals
|
|
. sys_clk (app_clk ),
|
|
. s_reset_n (app_reset_n ),
|
|
|
|
. count_inc (rx_qcnt_inc ),
|
|
. count_dec (rx_qcnt_dec ),
|
|
|
|
. reg_sel (sw_wr_en_12 ),
|
|
. reg_wr_data (reg_wdata[3:0] ),
|
|
. reg_wr (wr_be[0] ), // Byte write not supported for cntr
|
|
|
|
. cntr_intr ( ),
|
|
. cntrout (rx_qcnt )
|
|
);
|
|
|
|
stat_counter #(4) u_tx_qcnt (
|
|
// Clock and Reset Signals
|
|
. sys_clk (app_clk ),
|
|
. s_reset_n (app_reset_n ),
|
|
|
|
. count_inc (tx_qcnt_inc ),
|
|
. count_dec (tx_qcnt_dec ),
|
|
|
|
. reg_sel (sw_wr_en_12 ),
|
|
. reg_wr_data (reg_wdata[11:8] ),
|
|
. reg_wr (wr_be[2] ), // Byte write not supported for cntr
|
|
|
|
. cntr_intr ( ),
|
|
. cntrout (tx_qcnt )
|
);
|
);
|
|
|
// reg_13 is free
|
assign reg_12[7:0] = {4'h0,rx_qcnt[3:0]};
|
|
assign reg_12[15:8] = {4'h0,tx_qcnt[3:0]};
|
|
|
generic_intr_stat_reg #(9) u_intr_stat (
|
generic_intr_stat_reg #(9) u_intr_stat (
|
//inputs
|
//inputs
|
. clk (app_clk ),
|
. clk (app_clk ),
|
. reset_n (app_reset_n ),
|
. reset_n (app_reset_n ),
|
