| Line 48... |
Line 48... |
rx_reset_n,
|
rx_reset_n,
|
reset_mdio_clk_n,
|
reset_mdio_clk_n,
|
app_reset_n,
|
app_reset_n,
|
|
|
app_clk,
|
app_clk,
|
app_send_pause_i,
|
|
app_send_pause_active_o,
|
|
app_send_jam_i,
|
|
|
|
// Reg Bus Interface Signal
|
// Reg Bus Interface Signal
|
reg_cs,
|
reg_cs,
|
reg_wr,
|
reg_wr,
|
reg_addr,
|
reg_addr,
|
| Line 125... |
Line 122... |
|
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
// Application Clock Related Declaration
|
// Application Clock Related Declaration
|
//-----------------------------------------------------------------------
|
//-----------------------------------------------------------------------
|
input app_clk;
|
input app_clk;
|
input app_send_pause_i;
|
|
output app_send_pause_active_o;
|
|
input app_send_jam_i;
|
|
|
|
// Conntrol Bus Sync with Application Clock
|
// Conntrol Bus Sync with Application Clock
|
//---------------------------------
|
//---------------------------------
|
// Reg Bus Interface Signal
|
// Reg Bus Interface Signal
|
//---------------------------------
|
//---------------------------------
|
| Line 249... |
Line 243... |
.rx_dt_wrt (rx_fifo_wr_o),
|
.rx_dt_wrt (rx_fifo_wr_o),
|
.rx_dt_out (rx_fifo_data_o),
|
.rx_dt_out (rx_fifo_data_o),
|
.rx_commit_wr (rx_commit_wr_o),
|
.rx_commit_wr (rx_commit_wr_o),
|
.commit_write_done (rx_commit_write_done_o),
|
.commit_write_done (rx_commit_write_done_o),
|
.rx_rewind_wr (rx_rewind_wr_o),
|
.rx_rewind_wr (rx_rewind_wr_o),
|
//transistor interface
|
|
.rx2tx_pause_tx (rx2tx_pause_o),
|
|
//mii interface
|
//mii interface
|
.phy_rx_clk (phy_rx_clk),
|
.phy_rx_clk (phy_rx_clk),
|
.mi2rx_strt_rcv (mi2rx_strt_rcv),
|
.mi2rx_strt_rcv (mi2rx_strt_rcv),
|
.mi2rx_rcv_vld (mi2rx_rcv_vld),
|
.mi2rx_rcv_vld (mi2rx_rcv_vld),
|
.mi2rx_rx_byte (mi2rx_rx_byte),
|
.mi2rx_rx_byte (mi2rx_rx_byte),
|
| Line 269... |
Line 261... |
//Config interface
|
//Config interface
|
.cf2rx_max_pkt_sz (cf2rx_max_pkt_sz),
|
.cf2rx_max_pkt_sz (cf2rx_max_pkt_sz),
|
.cf2rx_rx_ch_en (cf2rx_ch_en),
|
.cf2rx_rx_ch_en (cf2rx_ch_en),
|
.cf2rx_strp_pad_en (cf2rx_strp_pad_en),
|
.cf2rx_strp_pad_en (cf2rx_strp_pad_en),
|
.cf2rx_snd_crc (cf2rx_snd_crc),
|
.cf2rx_snd_crc (cf2rx_snd_crc),
|
.cf2rx_pause_en (cf2rx_pause_en),
|
|
.cf2rx_rcv_runt_pkt_en (cf2rx_runt_pkt_en),
|
.cf2rx_rcv_runt_pkt_en (cf2rx_runt_pkt_en),
|
.cf_macmode (cf_mac_mode_o),
|
.cf_macmode (cf_mac_mode_o),
|
.cf2df_dfl_single_rx (cf2df_dfl_single_rx),
|
.cf2df_dfl_single_rx (cf2df_dfl_single_rx),
|
.ap2rx_rx_fifo_err (rx_fifo_error_i),
|
.ap2rx_rx_fifo_err (rx_fifo_error_i),
|
//A200 change Port added for crs based flow control
|
//A200 change Port added for crs based flow control
|
.phy_crs (phy_crs),
|
.phy_crs (phy_crs)
|
//A200 change crs flow control enable signal
|
|
.crs_flow_control_enable (cfg_crs_flow_ctrl_enb_i),
|
|
//A200 change pause detected pulse for counter
|
|
.pause_frame_detected ()
|
|
);
|
);
|
|
|
wire [4:0] cf2md_regad,cf2md_phyad;
|
wire [4:0] cf2md_regad,cf2md_phyad;
|
wire [15:0] cf2md_datain,md2cf_data;
|
wire [15:0] cf2md_datain,md2cf_data;
|
|
|
| Line 380... |
Line 367... |
);
|
);
|
|
|
|
|
wire [7:0] cf2df_dfl_single;
|
wire [7:0] cf2df_dfl_single;
|
wire [47:0] cf_mac_sa;
|
wire [47:0] cf_mac_sa;
|
wire [15:0] cf2tx_pause_quanta;
|
|
wire cf2tx_force_bad_fcs;
|
wire cf2tx_force_bad_fcs;
|
wire cf2tx_tstate_mode;
|
|
wire set_fifo_undrn;
|
wire set_fifo_undrn;
|
|
|
g_tx_top U_tx_top (
|
g_tx_top U_tx_top (
|
.app_clk (app_clk) ,
|
.app_clk (app_clk) ,
|
.send_pause_active (app_send_pause_active_o),
|
|
.set_fifo_undrn (tx_set_fifo_undrn_o),
|
.set_fifo_undrn (tx_set_fifo_undrn_o),
|
|
|
//Outputs
|
//Outputs
|
//TX FIFO management
|
//TX FIFO management
|
.tx_commit_read (tx_commit_read_o),
|
.tx_commit_read (tx_commit_read_o),
|
| Line 412... |
Line 396... |
//Inputs
|
//Inputs
|
//MII interface
|
//MII interface
|
.phy_tx_en (phy_tx_en),
|
.phy_tx_en (phy_tx_en),
|
.phy_tx_er (phy_tx_er),
|
.phy_tx_er (phy_tx_er),
|
|
|
//application
|
|
.app_send_pause (app_send_pause_i),
|
|
|
|
//rx_top
|
|
.rx2tx_pause (rx2tx_pause_o),
|
|
|
|
//configuration
|
//configuration
|
.cf2tx_tstate_mode (cf2tx_tstate_mode),
|
|
.cf2tx_ch_en (cf2tx_ch_en),
|
.cf2tx_ch_en (cf2tx_ch_en),
|
.cf2df_dfl_single (cf2df_dfl_single),
|
.cf2df_dfl_single (cf2df_dfl_single),
|
.cf2tx_pad_enable (cf2tx_pad_enable),
|
.cf2tx_pad_enable (cf2tx_pad_enable),
|
.cf2tx_append_fcs (cf2tx_append_fcs),
|
.cf2tx_append_fcs (cf2tx_append_fcs),
|
.cf_mac_mode (cf_mac_mode_o),
|
.cf_mac_mode (cf_mac_mode_o),
|
.cf_mac_sa (cf_mac_sa),
|
.cf_mac_sa (cf_mac_sa),
|
.cf2tx_pause_quanta (cf2tx_pause_quanta),
|
|
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
|
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
|
|
|
//FIFO data
|
//FIFO data
|
.app_tx_dt_in (tx_fifo_data_i),
|
.app_tx_dt_in (tx_fifo_data_i),
|
.app_tx_fifo_empty (tx_fifo_empty_i),
|
.app_tx_fifo_empty (tx_fifo_empty_i),
|
| Line 515... |
Line 492... |
.cf_silent_mode (cf_silent_mode),
|
.cf_silent_mode (cf_silent_mode),
|
.cf2mi_rmii_en (cf2mi_rmii_en_o),
|
.cf2mi_rmii_en (cf2mi_rmii_en_o),
|
|
|
// Config In
|
// Config In
|
.cfg_uni_mac_mode_change_i (cfg_uni_mac_mode_change_i),
|
.cfg_uni_mac_mode_change_i (cfg_uni_mac_mode_change_i),
|
.cfg_crs_flow_ctrl_enb_i (cfg_crs_flow_ctrl_enb_i),
|
|
|
|
//CHANNEL enable
|
//CHANNEL enable
|
.cf2tx_tstate_mode (cf2tx_tstate_mode),
|
|
.cf2tx_ch_en (cf2tx_ch_en),
|
.cf2tx_ch_en (cf2tx_ch_en),
|
//CHANNEL CONTROL TX
|
//CHANNEL CONTROL TX
|
.cf2df_dfl_single (cf2df_dfl_single),
|
.cf2df_dfl_single (cf2df_dfl_single),
|
.cf2df_dfl_single_rx (cf2df_dfl_single_rx),
|
.cf2df_dfl_single_rx (cf2df_dfl_single_rx),
|
.cf2tx_pad_enable (cf2tx_pad_enable),
|
.cf2tx_pad_enable (cf2tx_pad_enable),
|
| Line 530... |
Line 505... |
//CHANNEL CONTROL RX
|
//CHANNEL CONTROL RX
|
.cf2rx_max_pkt_sz (cf2rx_max_pkt_sz),
|
.cf2rx_max_pkt_sz (cf2rx_max_pkt_sz),
|
.cf2rx_ch_en (cf2rx_ch_en),
|
.cf2rx_ch_en (cf2rx_ch_en),
|
.cf2rx_strp_pad_en (cf2rx_strp_pad_en),
|
.cf2rx_strp_pad_en (cf2rx_strp_pad_en),
|
.cf2rx_snd_crc (cf2rx_snd_crc),
|
.cf2rx_snd_crc (cf2rx_snd_crc),
|
.cf2rx_pause_en (cf2rx_pause_en),
|
|
.cf2rx_addrchk_en (),
|
|
.cf2rx_runt_pkt_en (cf2rx_runt_pkt_en),
|
.cf2rx_runt_pkt_en (cf2rx_runt_pkt_en),
|
.cf2af_broadcast_disable (cf2af_broadcast_disable),
|
|
.cf_mac_sa (cf_mac_sa),
|
.cf_mac_sa (cf_mac_sa),
|
.cfg_ip_sa (cfg_ip_sa),
|
.cfg_ip_sa (cfg_ip_sa),
|
.cfg_mac_filter (cfg_mac_filter),
|
.cfg_mac_filter (cfg_mac_filter),
|
.cf2tx_pause_quanta (cf2tx_pause_quanta),
|
|
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
|
.cf2tx_force_bad_fcs (cf2tx_force_bad_fcs),
|
//MDIO CONTROL & DATA
|
//MDIO CONTROL & DATA
|
.cf2md_datain (cf2md_datain),
|
.cf2md_datain (cf2md_datain),
|
.cf2md_regad (cf2md_regad),
|
.cf2md_regad (cf2md_regad),
|
.cf2md_phyad (cf2md_phyad),
|
.cf2md_phyad (cf2md_phyad),
|
| Line 587... |
Line 558... |
.cf_chk_rx_dfl (cf_chk_rx_dfl),
|
.cf_chk_rx_dfl (cf_chk_rx_dfl),
|
.cf_silent_mode (cf_silent_mode),
|
.cf_silent_mode (cf_silent_mode),
|
|
|
// Signal from Application to transmit JAM
|
// Signal from Application to transmit JAM
|
.df2rx_dfl_dn (df2rx_dfl_dn),
|
.df2rx_dfl_dn (df2rx_dfl_dn),
|
.app_send_jam (app_send_jam_i),
|
|
|
|
// Inputs from Transmit FSM
|
// Inputs from Transmit FSM
|
.tx2mi_strt_preamble (tx2mi_strt_preamble),
|
.tx2mi_strt_preamble (tx2mi_strt_preamble),
|
.tx2mi_end_transmit (tx2mi_end_transmit),
|
.tx2mi_end_transmit (tx2mi_end_transmit),
|
.tx2mi_tx_byte (tx2mi_tx_byte),
|
.tx2mi_tx_byte (tx2mi_tx_byte),
|
