| Line 92... |
Line 92... |
cf_mac_mode,
|
cf_mac_mode,
|
cf_chk_rx_dfl,
|
cf_chk_rx_dfl,
|
cf_silent_mode,
|
cf_silent_mode,
|
|
|
// Signal from Application to transmit JAM
|
// Signal from Application to transmit JAM
|
app_send_jam,
|
|
df2rx_dfl_dn,
|
df2rx_dfl_dn,
|
|
|
// Inputs from Transmit FSM
|
// Inputs from Transmit FSM
|
tx2mi_strt_preamble,
|
tx2mi_strt_preamble,
|
tx2mi_end_transmit,
|
tx2mi_end_transmit,
|
| Line 150... |
Line 149... |
input cf2mi_loopback_en; // loop back enable
|
input cf2mi_loopback_en; // loop back enable
|
input cf2mi_rmii_en; // RMII Mode
|
input cf2mi_rmii_en; // RMII Mode
|
input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
|
input cf_mac_mode; // Mac Mode 0--> 10/100 Mode, 1--> 1000 Mode
|
input cf_chk_rx_dfl; // Check for Deferal
|
input cf_chk_rx_dfl; // Check for Deferal
|
input cf_silent_mode; // PHY Inactive
|
input cf_silent_mode; // PHY Inactive
|
input app_send_jam; // Send a Jam Sequence (From the Application)
|
|
input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
|
input df2rx_dfl_dn; // Deferal Done in Rx Clock Domain
|
input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
|
input tx2mi_strt_preamble; // Tx FSM indicates to MII to generate
|
// preamble on the line
|
// preamble on the line
|
input tx2mi_end_transmit; // This is provided by the TX block to
|
input tx2mi_end_transmit; // This is provided by the TX block to
|
// indicate end of transmit
|
// indicate end of transmit
|
| Line 177... |
Line 175... |
reg mi2rx_frame_err;
|
reg mi2rx_frame_err;
|
|
|
/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
|
/*** REG & WIRE DECLARATIONS FOR LOCAL SIGNALS ***************/
|
|
|
reg [4:0] tx_preamble_cnt_val;
|
reg [4:0] tx_preamble_cnt_val;
|
reg [4:0] jam_count;
|
|
reg [4:0] jam_count_reg;
|
|
|
|
|
|
reg strt_rcv_in;
|
reg strt_rcv_in;
|
reg end_rcv_in;
|
reg end_rcv_in;
|
reg rx_dv_in;
|
reg rx_dv_in;
|
| Line 200... |
Line 196... |
reg [2:0] mii_rx_nxt_st;
|
reg [2:0] mii_rx_nxt_st;
|
reg [2:0] mii_rx_cur_st;
|
reg [2:0] mii_rx_cur_st;
|
|
|
parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
|
parameter mii_tx_idle_st = 4'd0, mii_tx_pre_st = 4'd1,
|
mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
|
mii_tx_byte_st = 4'd2, mii_tx_end_st = 4'd3,
|
mii_tx_jam_st = 4'd4, mii_tx_nibble_st = 4'd5,
|
mii_tx_nibble_st = 4'd5,
|
mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
|
mii_tx_nibble_end_st = 4'd6, mii_tx_dibit_st = 4'd7,
|
mii_tx_dibit_end_st = 4'd8;
|
mii_tx_dibit_end_st = 4'd8;
|
|
|
reg [3:0] mii_tx_cur_st;
|
reg [3:0] mii_tx_cur_st;
|
reg [3:0] mii_tx_nxt_st;
|
reg [3:0] mii_tx_nxt_st;
|
|
|
wire send_jam;
|
|
wire receive_detect;
|
wire receive_detect;
|
wire pre_condition;
|
wire pre_condition;
|
wire sfd_condition;
|
wire sfd_condition;
|
wire tx_en;
|
wire tx_en;
|
wire tx_er;
|
wire tx_er;
|
| Line 221... |
Line 216... |
reg tx_en_in;
|
reg tx_en_in;
|
reg tx_err_in;
|
reg tx_err_in;
|
reg tx_ext_in;
|
reg tx_ext_in;
|
reg tx_pre_in;
|
reg tx_pre_in;
|
reg tx_sfd_in;
|
reg tx_sfd_in;
|
reg tx_jam_in;
|
|
reg tx_xfr_ack_in;
|
reg tx_xfr_ack_in;
|
reg inc_preamble_cntr;
|
reg inc_preamble_cntr;
|
reg rst_preamble_cntr;
|
reg rst_preamble_cntr;
|
reg inc_jam_cntr;
|
|
reg rst_jam_cntr;
|
|
reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
|
reg [1:0] tx_xfr_cnt, rx_xfr_cnt, tx_slot_xfr_cnt;
|
reg rx_dv;
|
reg rx_dv;
|
reg rx_er;
|
reg rx_er;
|
reg rcv_err_in;
|
reg rcv_err_in;
|
reg mi2rx_end_frame_in;
|
reg mi2rx_end_frame_in;
|
| Line 306... |
Line 298... |
end
|
end
|
end
|
end
|
|
|
always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
|
always @(mii_tx_cur_st or tx2mi_strt_preamble or tx2mi_end_transmit or cf_mac_mode
|
or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
|
or cf2mi_rmii_en or tx_preamble_cnt_val or byte_boundary_tx
|
or jam_count or tx_xfr_cnt or send_jam or receive_detect
|
or tx_xfr_cnt or receive_detect
|
or receive_detect_pulse or jam_count_reg or jam_count or cfg_uni_mac_mode_change)
|
or receive_detect_pulse or cfg_uni_mac_mode_change)
|
begin
|
begin
|
|
|
mii_tx_nxt_st = mii_tx_cur_st;
|
mii_tx_nxt_st = mii_tx_cur_st;
|
tx_en_in = 1'b0;
|
tx_en_in = 1'b0;
|
tx_pre_in = 1'b0;
|
tx_pre_in = 1'b0;
|
tx_sfd_in = 1'b0;
|
tx_sfd_in = 1'b0;
|
tx_err_in = 1'b0;
|
tx_err_in = 1'b0;
|
tx_ext_in = 1'b0;
|
tx_ext_in = 1'b0;
|
tx_jam_in = 1'b0;
|
|
inc_preamble_cntr = 1'b0;
|
inc_preamble_cntr = 1'b0;
|
rst_preamble_cntr = 1'b0;
|
rst_preamble_cntr = 1'b0;
|
inc_jam_cntr = 1'b0;
|
|
rst_jam_cntr = 1'b0;
|
|
tx_xfr_ack_in = 1'b0;
|
tx_xfr_ack_in = 1'b0;
|
|
|
casex(mii_tx_cur_st) // synopsys parallel_case full_case
|
casex(mii_tx_cur_st) // synopsys parallel_case full_case
|
|
|
mii_tx_idle_st:
|
mii_tx_idle_st:
|
| Line 420... |
Line 409... |
tx_xfr_ack_in = 1'b1;
|
tx_xfr_ack_in = 1'b1;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
mii_tx_nxt_st = mii_tx_byte_st;
|
end
|
end
|
end*/
|
end*/
|
|
|
mii_tx_jam_st:
|
|
begin
|
|
if(jam_count == jam_count_reg)
|
|
begin
|
|
tx_en_in = 1'b1;
|
|
tx_jam_in = 1'b1;
|
|
rst_jam_cntr = 1'b1;
|
|
mii_tx_nxt_st = mii_tx_idle_st;
|
|
end
|
|
else
|
|
begin
|
|
tx_en_in = 1'b1;
|
|
tx_jam_in = 1'b1;
|
|
inc_jam_cntr = 1'b1;
|
|
mii_tx_nxt_st = mii_tx_jam_st;
|
|
end
|
|
end
|
|
|
|
mii_tx_end_st:
|
mii_tx_end_st:
|
// This state checks for the end of transfer
|
// This state checks for the end of transfer
|
// and extend for carrier extension
|
// and extend for carrier extension
|
begin
|
begin
|
if(tx2mi_strt_preamble)
|
if(tx2mi_strt_preamble)
|
| Line 588... |
Line 559... |
end
|
end
|
else
|
else
|
begin
|
begin
|
if (cf_mac_mode)
|
if (cf_mac_mode)
|
phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
|
phy_txd[7:0] <= (tx_pre_in) ? 8'b01010101 : ((tx_sfd_in) ?
|
8'b11010101 : ((tx_jam_in) ? 8'b11111111 :
|
8'b11010101 : ((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte));
|
((tx_ext_in) ? 8'b00001111: tx2mi_tx_byte)));
|
|
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
else if (!cf_mac_mode && !cf2mi_rmii_en)
|
phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
|
phy_txd[3:0] <= (tx_pre_in) ? 4'b0101 : ((tx_sfd_in) ?
|
4'b1101 : ((tx_jam_in) ? 4'b1111 : tx_nibble_in)) ;
|
4'b1101 : tx_nibble_in) ;
|
else if (!cf_mac_mode && cf2mi_rmii_en)
|
else if (!cf_mac_mode && cf2mi_rmii_en)
|
phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
|
phy_txd[1:0] <= (tx_pre_in) ? 2'b01 : ((tx_sfd_in) ?
|
2'b11 : ((tx_jam_in) ? 2'b11 : tx_dibit_in)) ;
|
2'b11 : tx_dibit_in) ;
|
end
|
end
|
end
|
end
|
assign receive_detect_pulse = receive_detect && !d_receive_detect;
|
assign receive_detect_pulse = receive_detect && !d_receive_detect;
|
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
|
begin
|
|
if(!tx_reset_n)
|
|
jam_count_reg <= 5'd0;
|
|
else if(cf_mac_mode)
|
|
jam_count_reg <= GMII_JAM_COUNT;
|
|
else if(cf2mi_rmii_en)
|
|
jam_count_reg <= RMII_JAM_COUNT;
|
|
else if(!cf2mi_rmii_en)
|
|
jam_count_reg <= MII_JAM_COUNT;
|
|
end
|
|
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
begin
|
begin
|
if(!tx_reset_n)
|
if(!tx_reset_n)
|
d_receive_detect <= 0;
|
d_receive_detect <= 0;
|
| Line 706... |
Line 665... |
tx_preamble_cnt_val <= 5'd0;
|
tx_preamble_cnt_val <= 5'd0;
|
else if(inc_preamble_cntr)
|
else if(inc_preamble_cntr)
|
tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
|
tx_preamble_cnt_val <= tx_preamble_cnt_val + 1;
|
end
|
end
|
|
|
// Jam Counter
|
|
always @(posedge phy_tx_clk or negedge tx_reset_n)
|
|
begin
|
|
if(!tx_reset_n)
|
|
jam_count <= 5'd0;
|
|
else if(rst_jam_cntr)
|
|
jam_count <= 5'd0;
|
|
else if(inc_jam_cntr)
|
|
jam_count <= jam_count + 1;
|
|
end
|
|
|
|
|
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
always @(posedge phy_rx_clk or negedge rx_reset_n)
|
begin
|
begin
|
if(!rx_reset_n)
|
if(!rx_reset_n)
|
| Line 1005... |
Line 954... |
rx_dv_del <= rx_dv;
|
rx_dv_del <= rx_dv;
|
end
|
end
|
end
|
end
|
|
|
|
|
half_dup_dble_reg U_dble_reg0 (
|
|
//outputs
|
|
.sync_out_pulse(send_jam),
|
|
//inputs
|
|
.in_pulse(app_send_jam),
|
|
.dest_clk(phy_tx_clk),
|
|
.reset_n(tx_reset_n)
|
|
);
|
|
|
|
half_dup_dble_reg U_dble_reg1 (
|
half_dup_dble_reg U_dble_reg1 (
|
//outputs
|
//outputs
|
.sync_out_pulse(receive_detect),
|
.sync_out_pulse(receive_detect),
|
//inputs
|
//inputs
|
