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//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Mar 2, 2011 ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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CRC and Address Filtering block. It also generates the necessary
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CRC and Address Filtering block. It also generates the necessary
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signals to generate status for every frame.
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signals to generate status for every frame.
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***************************************************************/
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***************************************************************/
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/************** MODULE DECLARATION ****************************/
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/************** MODULE DECLARATION ****************************/
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//`timescale 1ns/100ps
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module g_rx_fsm(
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module g_rx_fsm(
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// Status information to Applications
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// Status information to Applications
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rx_sts_vld,
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rx_sts_vld,
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rx_sts_bytes_rcvd,
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rx_sts_bytes_rcvd,
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rx_sts_large_pkt,
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rx_sts_large_pkt,
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end // if (rx_ch_en)
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end // if (rx_ch_en)
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end // else: !if(!reset_n)
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end // else: !if(!reset_n)
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end // always @ (posedge phy_rx_clk...
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end // always @ (posedge phy_rx_clk...
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endmodule
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endmodule
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