| Line 62... |
Line 62... |
rx_dt_wrt,
|
rx_dt_wrt,
|
rx_dt_out,
|
rx_dt_out,
|
rx_commit_wr,
|
rx_commit_wr,
|
commit_write_done,
|
commit_write_done,
|
rx_rewind_wr,
|
rx_rewind_wr,
|
rx2tx_pause_tx,
|
|
mi2rx_strt_rcv,
|
mi2rx_strt_rcv,
|
mi2rx_rcv_vld,
|
mi2rx_rcv_vld,
|
mi2rx_rx_byte,
|
mi2rx_rx_byte,
|
mi2rx_end_rcv,
|
mi2rx_end_rcv,
|
mi2rx_extend,
|
mi2rx_extend,
|
| Line 75... |
Line 74... |
phy_rx_dv,
|
phy_rx_dv,
|
cf2rx_max_pkt_sz,
|
cf2rx_max_pkt_sz,
|
cf2rx_rx_ch_en,
|
cf2rx_rx_ch_en,
|
cf2rx_strp_pad_en,
|
cf2rx_strp_pad_en,
|
cf2rx_snd_crc,
|
cf2rx_snd_crc,
|
cf2rx_pause_en,
|
|
cf2df_dfl_single_rx,
|
cf2df_dfl_single_rx,
|
cf2rx_rcv_runt_pkt_en,
|
cf2rx_rcv_runt_pkt_en,
|
cf_macmode,
|
cf_macmode,
|
mi2rx_crs,
|
mi2rx_crs,
|
df2rx_dfl_dn,
|
df2rx_dfl_dn,
|
ap2rx_rx_fifo_err,
|
ap2rx_rx_fifo_err,
|
//A200 change Port added for crs based flow control
|
//A200 change Port added for crs based flow control
|
phy_crs,
|
phy_crs
|
//A200 change crs flow control enable signal
|
|
crs_flow_control_enable,
|
|
//A200 change pause detected pulse for counter
|
|
pause_frame_detected
|
|
);
|
);
|
|
|
input app_reset_n;
|
input app_reset_n;
|
input phy_rx_clk;
|
input phy_rx_clk;
|
input rx_reset_n;
|
input rx_reset_n;
|
| Line 113... |
Line 107... |
output rx_dt_wrt;
|
output rx_dt_wrt;
|
output [8:0] rx_dt_out;
|
output [8:0] rx_dt_out;
|
output rx_commit_wr;
|
output rx_commit_wr;
|
output commit_write_done;
|
output commit_write_done;
|
output rx_rewind_wr;
|
output rx_rewind_wr;
|
output rx2tx_pause_tx;
|
|
input mi2rx_strt_rcv;
|
input mi2rx_strt_rcv;
|
input mi2rx_rcv_vld;
|
input mi2rx_rcv_vld;
|
input [7:0] mi2rx_rx_byte;
|
input [7:0] mi2rx_rx_byte;
|
input mi2rx_end_rcv;
|
input mi2rx_end_rcv;
|
input mi2rx_extend;
|
input mi2rx_extend;
|
| Line 126... |
Line 119... |
input phy_rx_dv;
|
input phy_rx_dv;
|
input [15:0] cf2rx_max_pkt_sz;
|
input [15:0] cf2rx_max_pkt_sz;
|
input cf2rx_rx_ch_en;
|
input cf2rx_rx_ch_en;
|
input cf2rx_strp_pad_en;
|
input cf2rx_strp_pad_en;
|
input cf2rx_snd_crc;
|
input cf2rx_snd_crc;
|
input cf2rx_pause_en;
|
|
input cf2rx_rcv_runt_pkt_en;
|
input cf2rx_rcv_runt_pkt_en;
|
input cf_macmode;
|
input cf_macmode;
|
input [7:0] cf2df_dfl_single_rx;
|
input [7:0] cf2df_dfl_single_rx;
|
input ap2rx_rx_fifo_err;
|
input ap2rx_rx_fifo_err;
|
input mi2rx_crs;
|
input mi2rx_crs;
|
output df2rx_dfl_dn;
|
output df2rx_dfl_dn;
|
|
|
//A200 change Port added for crs based flow control
|
//A200 change Port added for crs based flow control
|
input phy_crs;
|
input phy_crs;
|
//A200 change crs flow control enable signal
|
|
input crs_flow_control_enable;
|
|
|
|
//A200 change pause detected pulse for counter
|
|
output pause_frame_detected;
|
|
|
|
|
|
g_rx_fsm u_rx_fsm(
|
g_rx_fsm u_rx_fsm(
|
// Status information to Applications
|
// Status information to Applications
|
.rx_sts_vld(rx_sts_vld),
|
.rx_sts_vld(rx_sts_vld),
|
| Line 162... |
Line 150... |
.rx2ap_rx_fsm_dt(rx_dt_out),
|
.rx2ap_rx_fsm_dt(rx_dt_out),
|
// Fifo Control Signal to Fifo Management Block
|
// Fifo Control Signal to Fifo Management Block
|
.rx2ap_commit_write(rx_commit_wr),
|
.rx2ap_commit_write(rx_commit_wr),
|
.rx2ap_rewind_write(rx_rewind_wr),
|
.rx2ap_rewind_write(rx_rewind_wr),
|
// To address filtering block
|
// To address filtering block
|
// Pause control to Tx block
|
|
.rx2tx_pause_tx(rx2tx_pause_tx),
|
|
.commit_write_done(commit_write_done),
|
.commit_write_done(commit_write_done),
|
|
|
// Global Signals
|
// Global Signals
|
.reset_n(rx_reset_n),
|
.reset_n(rx_reset_n),
|
.phy_rx_clk(phy_rx_clk),
|
.phy_rx_clk(phy_rx_clk),
|
| Line 183... |
Line 169... |
.rx_fifo_full(rx_fifo_full),
|
.rx_fifo_full(rx_fifo_full),
|
.ap2rx_rx_fifo_err(ap2rx_rx_fifo_err),
|
.ap2rx_rx_fifo_err(ap2rx_rx_fifo_err),
|
// Signal from CRC check block
|
// Signal from CRC check block
|
.rc2rx_crc_ok(rc2rx_crc_ok),
|
.rc2rx_crc_ok(rc2rx_crc_ok),
|
// Signals from Address filtering block
|
// Signals from Address filtering block
|
.af2rx_pause_frame(af2rx_pause_frame),
|
|
// Signals from Config Management Block
|
// Signals from Config Management Block
|
.cf2rx_max_pkt_sz(cf2rx_max_pkt_sz),
|
.cf2rx_max_pkt_sz(cf2rx_max_pkt_sz),
|
.cf2rx_rx_ch_en(cf2rx_rx_ch_en),
|
.cf2rx_rx_ch_en(cf2rx_rx_ch_en),
|
.cf2rx_strp_pad_en(cf2rx_strp_pad_en),
|
.cf2rx_strp_pad_en(cf2rx_strp_pad_en),
|
.cf2rx_snd_crc(cf2rx_snd_crc),
|
.cf2rx_snd_crc(cf2rx_snd_crc),
|
.cf2rx_pause_en(cf2rx_pause_en),
|
|
.cf2rx_rcv_runt_pkt_en(cf2rx_rcv_runt_pkt_en),
|
.cf2rx_rcv_runt_pkt_en(cf2rx_rcv_runt_pkt_en),
|
.cf2rx_gigabit_xfr(cf_macmode),
|
.cf2rx_gigabit_xfr(cf_macmode),
|
//A200 change Port added for crs based flow control
|
//A200 change Port added for crs based flow control
|
.phy_crs(phy_crs),
|
.phy_crs(phy_crs)
|
//A200 change crs flow control enable signal
|
|
.crs_flow_control_enable(crs_flow_control_enable),
|
|
//A200 change pause detected pulse for counter
|
|
.pause_frame_detected(pause_frame_detected)
|
|
);
|
);
|
|
|
g_ad_fltr u_ad_fltr(
|
|
.phy_rx_clk(phy_rx_clk),
|
|
.rx_reset_n(rx_reset_n),
|
|
.app_clk(app_clk),
|
|
.scan_mode(scan_mode),
|
|
//MII Interface
|
|
.mi2af_rcv_vld(mi2rx_rcv_vld),
|
|
.mi2af_strt_rcv(mi2rx_strt_rcv),
|
|
.mi2af_end_rcv(mi2rx_end_rcv),
|
|
.mi2af_rx_data(mi2rx_rx_byte),
|
|
//RX_FSM Interface
|
|
.af2rf_pause_frame(af2rx_pause_frame)
|
|
);
|
|
|
|
g_rx_crc32 u_rx_crc32 (
|
g_rx_crc32 u_rx_crc32 (
|
// CRC Valid signal to rx_fsm
|
// CRC Valid signal to rx_fsm
|
.rc2rf_crc_ok(rc2rx_crc_ok),
|
.rc2rf_crc_ok(rc2rx_crc_ok),
|
|
|
