| Line 157... |
Line 157... |
output [7:0] tx2mi_byte; //data to RMII and MII interface
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output [7:0] tx2mi_byte; //data to RMII and MII interface
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output tx2mi_end_transmit; //frame transfer done
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output tx2mi_end_transmit; //frame transfer done
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output tx_sts_vld; //tx status is valid
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output tx_sts_vld; //tx status is valid
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output [15:0] tx_sts_byte_cntr;
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output [15:0] tx_sts_byte_cntr;
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output tx_sts_fifo_underrun;
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output tx_sts_fifo_underrun;
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output tx_ch_en; // MANDAR
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output tx_ch_en;
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input phy_tx_en; // mfilardo ofn auth fix.
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input phy_tx_en;
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input app_clk;
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input app_clk;
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output set_fifo_undrn; // Description: At GMII Interface ,
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output set_fifo_undrn;
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// abug after a transmit fifo underun was found.
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// The packet after a packet that
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// underran has 1 too few bytes .
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parameter mn_idle_st = 3'd0;
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parameter mn_idle_st = 3'd0;
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parameter mn_snd_full_dup_frm_st = 3'd1;
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parameter mn_snd_full_dup_frm_st = 3'd1;
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| Line 213... |
Line 210... |
reg frm_padded; //current frame is padded
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reg frm_padded; //current frame is padded
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reg set_pad_byte; //send zero filled bytes
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reg set_pad_byte; //send zero filled bytes
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reg e_tx_sts_vld; //current packet is transferred
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reg e_tx_sts_vld; //current packet is transferred
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reg tx_sts_vld; //02999
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reg tx_sts_vld;
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reg strt_preamble;
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reg strt_preamble;
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reg [7:0] tx_byte;
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reg [7:0] tx_byte;
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reg [7:0] tx_fsm_dt_reg;
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reg [7:0] tx_fsm_dt_reg;
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reg tx_end_frame_reg;
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reg tx_end_frame_reg;
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reg tx_lst_xfr_dt, tx_lst_xfr_fcs;
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reg tx_lst_xfr_dt, tx_lst_xfr_fcs;
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| Line 569... |
Line 566... |
end // always
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end // always
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wire strt_preamble_prog;
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wire strt_preamble_prog;
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assign strt_preamble_pls = strt_preamble || s_p_d1 || s_p_d2 || s_p_d3;
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assign strt_preamble_pls = strt_preamble || s_p_d1 || s_p_d2 || s_p_d3;
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assign strt_preamble_prog = strt_preamble;
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assign strt_preamble_prog = strt_preamble;
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//ECO fix, part1 end
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//fsm to transmit the FCS
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//fsm to transmit the FCS
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//synchronous process
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//synchronous process
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always @(posedge tx_clk or negedge tx_reset_n)
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always @(posedge tx_clk or negedge tx_reset_n)
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begin
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begin
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| Line 620... |
Line 616... |
begin
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begin
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if (!tx_reset_n)
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if (!tx_reset_n)
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begin
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begin
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strt_fcs_reg <= 0;
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strt_fcs_reg <= 0;
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tx_fcs_dn_reg <= 0;
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tx_fcs_dn_reg <= 0;
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tx_lst_xfr_fcs_reg <= 0; //naveen 052799
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tx_lst_xfr_fcs_reg <= 0;
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end // if (!tx_reset_n)
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end // if (!tx_reset_n)
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else
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else
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begin
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begin
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tx_fcs_dn_reg <= tx_fcs_dn;
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tx_fcs_dn_reg <= tx_fcs_dn;
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strt_fcs_reg <= strt_fcs;
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strt_fcs_reg <= strt_fcs;
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tx_lst_xfr_fcs_reg <= tx_lst_xfr_fcs; //naveen 052799
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tx_lst_xfr_fcs_reg <= tx_lst_xfr_fcs;
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end // else: !if(!tx_reset_n)
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end // else: !if(!tx_reset_n)
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end // always @ (posedge tx_clk or negedge tx_reset_n)
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end // always @ (posedge tx_clk or negedge tx_reset_n)
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//combinatorial process
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//combinatorial process
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//bad fcs or good fcs could have been requested, in either case
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//bad fcs or good fcs could have been requested, in either case
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| Line 683... |
Line 679... |
else if (mi2tx_byte_ack)
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else if (mi2tx_byte_ack)
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fcs_mux_select <= fcs_mux_select + 1 ;
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fcs_mux_select <= fcs_mux_select + 1 ;
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end // else: !if(!tx_reset_n)
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end // else: !if(!tx_reset_n)
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end // always @ (posedge tx_clk or negedge tx_reset_n)
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end // always @ (posedge tx_clk or negedge tx_reset_n)
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//remmember if frame is padded
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//if frame is padded
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always @(posedge tx_clk or negedge tx_reset_n)
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always @(posedge tx_clk or negedge tx_reset_n)
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begin
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begin
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if (!tx_reset_n)
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if (!tx_reset_n)
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frm_padded <= 0;
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frm_padded <= 0;
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else
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else
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