| Line 53... |
Line 53... |
4. deferral
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4. deferral
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5. backoff
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5. backoff
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***********************************************************************/
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***********************************************************************/
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module g_tx_top(
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module g_tx_top(
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app_clk,
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app_clk,
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send_pause_active,
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set_fifo_undrn,
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set_fifo_undrn,
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//Outputs
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//Outputs
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//TX FIFO management
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//TX FIFO management
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| Line 79... |
Line 78... |
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//Inputs
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//Inputs
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//MII interface
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//MII interface
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phy_tx_en,
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phy_tx_en,
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phy_tx_er,
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phy_tx_er,
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//application
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app_send_pause,
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//rx_top
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rx2tx_pause,
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//configuration
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//configuration
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cf2tx_tstate_mode,
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cf2tx_ch_en,
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cf2tx_ch_en,
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cf2df_dfl_single,
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cf2df_dfl_single,
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cf2tx_pad_enable,
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cf2tx_pad_enable,
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cf2tx_append_fcs,
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cf2tx_append_fcs,
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cf_mac_mode,
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cf_mac_mode,
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cf_mac_sa,
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cf_mac_sa,
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cf2tx_pause_quanta,
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cf2tx_force_bad_fcs,
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cf2tx_force_bad_fcs,
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//FIFO data
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//FIFO data
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app_tx_dt_in,
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app_tx_dt_in,
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app_tx_fifo_empty,
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app_tx_fifo_empty,
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app_tx_rdy,
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app_tx_rdy,
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| Line 109... |
Line 101... |
tx_clk);
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tx_clk);
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input app_reset_n; // Global app_reset for the MAC
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input app_reset_n; // Global app_reset for the MAC
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input tx_reset_n;
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input tx_reset_n;
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input tx_clk; // Transmit clock
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input tx_clk; // Transmit clock
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input app_send_pause;
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input [8:0] app_tx_dt_in;
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input [8:0] app_tx_dt_in;
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input app_tx_fifo_empty;
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input app_tx_fifo_empty;
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input app_tx_rdy;
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input app_tx_rdy;
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input phy_tx_en; // Transmit data Enable
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input phy_tx_en; // Transmit data Enable
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input phy_tx_er; // Transmit Error
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input phy_tx_er; // Transmit Error
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input cf2tx_tstate_mode; // OFN auth intf fix
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input cf2tx_ch_en; // Transmit channel Enable
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input cf2tx_ch_en; // Transmit channel Enable
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input [7:0] cf2df_dfl_single;
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input [7:0] cf2df_dfl_single;
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input cf2tx_pad_enable; // Padding Enabled
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input cf2tx_pad_enable; // Padding Enabled
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input cf2tx_append_fcs; // Append CRC to packets
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input cf2tx_append_fcs; // Append CRC to packets
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input cf2tx_force_bad_fcs; // force bad fcs
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input cf2tx_force_bad_fcs; // force bad fcs
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input [47:0] cf_mac_sa; // MAC Source Address
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input [47:0] cf_mac_sa; // MAC Source Address
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input [15:0] cf2tx_pause_quanta; // Pause Quanta used when sending a pause frame
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input cf_mac_mode; // Gigabit or 10/100
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input cf_mac_mode; // Gigabit or 10/100
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input rx2tx_pause;
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input mi2tx_byte_ack; // Transmit byte ack from RMII
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input mi2tx_byte_ack; // Transmit byte ack from RMII
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output tx_commit_read;
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output tx_commit_read;
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output tx_dt_rd; //get the next fsm data
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output tx_dt_rd; //get the next fsm data
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| Line 145... |
Line 133... |
output [15:0] tx_sts_byte_cntr;
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output [15:0] tx_sts_byte_cntr;
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output tx_sts_fifo_underrun;
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output tx_sts_fifo_underrun;
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output tx_ch_en; // MANDAR
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output tx_ch_en; // MANDAR
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output send_pause_active; // condor fix
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output set_fifo_undrn;// Description: At GMII Interface ,
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output set_fifo_undrn;// Description: At GMII Interface ,
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// abug after a transmit fifo underun was found.
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// abug after a transmit fifo underun was found.
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// The packet after a packet that
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// The packet after a packet that
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// underran has 1 too few bytes .
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// underran has 1 too few bytes .
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| Line 174... |
Line 161... |
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// Instantiate Transmit State machine block
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// Instantiate Transmit State machine block
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g_tx_fsm U_tx_fsm(
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g_tx_fsm U_tx_fsm(
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.send_pause_active_out(send_pause_active), // condor fix
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.app_clk(app_clk), // condor fix
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.app_clk(app_clk), // condor fix
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.set_fifo_undrn(set_fifo_undrn), // E3C fix
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.set_fifo_undrn(set_fifo_undrn), // E3C fix
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//Outputs
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//Outputs
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.tx_commit_read(tx_commit_read),
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.tx_commit_read(tx_commit_read),
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| Line 201... |
Line 187... |
.tx_end_frame(app_tx_dt_in[8]),
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.tx_end_frame(app_tx_dt_in[8]),
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.app_tx_dt_in(app_tx_dt_in[7:0]),
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.app_tx_dt_in(app_tx_dt_in[7:0]),
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.app_tx_fifo_empty(app_tx_fifo_empty),
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.app_tx_fifo_empty(app_tx_fifo_empty),
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//dfl and back off
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//dfl and back off
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.df2tx_dfl_dn(df2tx_dfl_dn),
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.df2tx_dfl_dn(df2tx_dfl_dn),
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.app_send_pause(app_send_pause),
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//inputs from FCS
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//inputs from FCS
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.tc2tx_fcs(tc2tx_fcs),
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.tc2tx_fcs(tc2tx_fcs),
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.cf2tx_tstate_mode(cf2tx_tstate_mode),
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.cf2tx_ch_en(cf2tx_ch_en),
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.cf2tx_ch_en(cf2tx_ch_en),
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.cf2tx_pad_enable(cf2tx_pad_enable),
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.cf2tx_pad_enable(cf2tx_pad_enable),
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.cf2tx_append_fcs(cf2tx_append_fcs),
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.cf2tx_append_fcs(cf2tx_append_fcs),
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.cf_mac_mode(cf_mac_mode),
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.cf_mac_mode(cf_mac_mode),
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.cf_mac_sa(cf_mac_sa),
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.cf_mac_sa(cf_mac_sa),
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.cf2tx_pause_quanta(cf2tx_pause_quanta),
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.cf2tx_force_bad_fcs(cf2tx_force_bad_fcs),
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.cf2tx_force_bad_fcs(cf2tx_force_bad_fcs),
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//RX pause frame received
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.rx2tx_pause(rx2tx_pause),
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//MII
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//MII
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.mi2tx_byte_ack(mi2tx_byte_ack),
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.mi2tx_byte_ack(mi2tx_byte_ack),
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.tx_clk(tx_clk),
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.tx_clk(tx_clk),
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.tx_reset_n(tx_reset_n),
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.tx_reset_n(tx_reset_n),
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.app_reset_n(app_reset_n));
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.app_reset_n(app_reset_n));
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