| Line 57... |
Line 57... |
app_clk,
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app_clk,
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// Application RX FIFO Interface
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// Application RX FIFO Interface
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app_txfifo_wren_i,
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app_txfifo_wren_i,
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app_txfifo_wrdata_i,
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app_txfifo_wrdata_i,
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app_txfifo_addr,
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app_txfifo_full_o,
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app_txfifo_full_o,
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app_txfifo_afull_o,
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app_txfifo_afull_o,
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app_txfifo_space_o,
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app_txfifo_space_o,
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// Application TX FIFO Interface
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// Application TX FIFO Interface
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app_rxfifo_rden_i,
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app_rxfifo_rden_i,
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app_rxfifo_empty_o,
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app_rxfifo_empty_o,
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app_rxfifo_aempty_o,
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app_rxfifo_aempty_o,
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app_rxfifo_cnt_o,
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app_rxfifo_cnt_o,
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app_rxfifo_rdata_o,
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app_rxfifo_rdata_o,
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app_rxfifo_addr,
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app_rx_desc_req ,
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app_rx_desc_ack ,
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app_rx_desc_discard ,
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app_rx_desc_data ,
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// Conntrol Bus Sync with Application Clock
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// Conntrol Bus Sync with Application Clock
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reg_cs,
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reg_cs,
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reg_wr,
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reg_wr,
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reg_addr,
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reg_addr,
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| Line 99... |
Line 106... |
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//MDIO interface
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//MDIO interface
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mdio_clk,
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mdio_clk,
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mdio_in,
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mdio_in,
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mdio_out_en,
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mdio_out_en,
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mdio_out
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mdio_out,
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// QCounter
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rx_buf_qbase_addr,
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tx_buf_qbase_addr,
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tx_qcnt_inc,
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tx_qcnt_dec,
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rx_qcnt_inc,
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rx_qcnt_dec,
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tx_qcnt,
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rx_qcnt
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);
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);
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parameter W = 8'd9;
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parameter W = 8'd9;
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parameter DP = 8'd32;
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parameter DP = 8'd32;
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parameter AW = (DP == 2) ? 1 :
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parameter AW = (DP == 2) ? 1 :
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| Line 133... |
Line 153... |
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// Application RX FIFO Interface
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// Application RX FIFO Interface
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input app_txfifo_wren_i;
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input app_txfifo_wren_i;
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input [8:0] app_txfifo_wrdata_i;
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input [8:0] app_txfifo_wrdata_i;
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output [15:0] app_txfifo_addr;
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output app_txfifo_full_o;
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output app_txfifo_full_o;
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output app_txfifo_afull_o;
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output app_txfifo_afull_o;
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output [AW:0] app_txfifo_space_o;
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output [AW:0] app_txfifo_space_o;
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// Application TX FIFO Interface
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// Application TX FIFO Interface
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input app_rxfifo_rden_i;
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input app_rxfifo_rden_i;
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output app_rxfifo_empty_o;
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output app_rxfifo_empty_o;
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output app_rxfifo_aempty_o;
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output app_rxfifo_aempty_o;
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output [AW:0] app_rxfifo_cnt_o;
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output [AW:0] app_rxfifo_cnt_o;
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output [8:0] app_rxfifo_rdata_o;
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output [8:0] app_rxfifo_rdata_o;
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output [15:0] app_rxfifo_addr;
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// descriptor interface
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output app_rx_desc_req ; // descriptor request
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input app_rx_desc_ack ; // descriptor ack
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output app_rx_desc_discard ; // descriptor discard
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output [31:0] app_rx_desc_data ; // descriptor data
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// Conntrol Bus Sync with Application Clock
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// Conntrol Bus Sync with Application Clock
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//---------------------------------
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//---------------------------------
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// Reg Bus Interface Signal
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// Reg Bus Interface Signal
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//---------------------------------
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//---------------------------------
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| Line 184... |
Line 213... |
input mdio_clk;
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input mdio_clk;
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input mdio_in;
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input mdio_in;
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output mdio_out_en;
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output mdio_out_en;
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output mdio_out;
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output mdio_out;
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//--------------------------------------
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// QCounter, Better to move to seperate global reg block
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//-------------------------------------
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output [9:0] rx_buf_qbase_addr; // Rx QBase Address
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output [9:0] tx_buf_qbase_addr; // TX QBase Address
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input tx_qcnt_inc; // Tx QCounter Increment indication
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input tx_qcnt_dec; // Tx QCounter Decrement indication
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input rx_qcnt_inc; // Rx QCounter Increment indication
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input rx_qcnt_dec; // Rx QCounter Decrement indication
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output [3:0] tx_qcnt ;
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output [3:0] rx_qcnt ;
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//---------------------
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//---------------------
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// RX FIFO Interface Signal
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// RX FIFO Interface Signal
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wire clr_rx_error_from_rx_fsm_o;
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wire clr_rx_error_from_rx_fsm_o;
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wire rx_fifo_full_i;
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wire rx_fifo_full_i;
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wire rx_fifo_wr_o;
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wire rx_fifo_wr_o;
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| Line 209... |
Line 252... |
wire [AW:0] tx_fifo_aval;
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wire [AW:0] tx_fifo_aval;
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wire [47:0] cf_mac_sa;
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wire [47:0] cf_mac_sa;
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wire [31:0] cfg_ip_sa;
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wire [31:0] cfg_ip_sa;
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wire [31:0] cfg_mac_filter;
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wire [31:0] cfg_mac_filter;
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wire [3:0] tx_buf_base_addr;
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wire [3:0] rx_buf_base_addr;
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wire [11:0] g_rx_pkt_len;
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wire [15:0] pkt_status;
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wire app_rxfifo_empty;
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wire g_rx_block_rxrd;
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assign app_rxfifo_empty_o = app_rxfifo_empty | g_rx_block_rxrd;
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g_dpath_ctrl m_g_dpath_ctrl (
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.rst_n ( s_reset_n ),
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.clk ( app_clk ),
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.rx_buf_base_addr (rx_buf_base_addr ),
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.tx_buf_base_addr (tx_buf_base_addr ),
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// gmac core to memory write interface
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.g_rx_mem_rd ( app_rxfifo_rden_i ),
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.g_rx_mem_eop ( app_rxfifo_rdata_o[8] ),
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.g_rx_mem_addr ( app_rxfifo_addr ),
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.g_rx_block_rxrd ( g_rx_block_rxrd ),
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// descr handshake
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.g_rx_desc_req (app_rx_desc_req ),
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.g_rx_desc_discard (app_rx_desc_discard ),
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.g_rx_desc_data (app_rx_desc_data ),
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.g_rx_desc_ack (app_rx_desc_ack ),
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.g_rx_pkt_done (g_rx_pkt_done ),
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.g_rx_pkt_len (g_rx_pkt_len ),
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.g_rx_pkt_status (g_rx_pkt_status ),
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.g_rx_pkt_drop (g_rx_pkt_drop )
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);
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g_eth_parser u_eth_parser (
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g_eth_parser u_eth_parser (
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.s_reset_n (app_reset_n),
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.s_reset_n (app_reset_n),
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.app_clk (app_clk),
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.app_clk (app_clk),
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// Configuration
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// Configuration
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.cfg_filters (cfg_filters),
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.cfg_filters (cfg_mac_filter),
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.cfg_mac_sa (cf_mac_sa),
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.cfg_mac_sa (cf_mac_sa),
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.cfg_ip_sa (cfg_ip_sa),
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.cfg_ip_sa (cfg_ip_sa),
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// Input Control Information
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// Input Control Information
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.eop (app_rxfifo_rdata_o[8]),
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.eop (app_rxfifo_rdata_o[8]),
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.dval (app_rxfifo_rden_i),
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.dval (app_rxfifo_rden_i),
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.data (app_rxfifo_rdata_o[7:0]),
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.data (app_rxfifo_rdata_o[7:0]),
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// output status
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// output status
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.pkt_done (),
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.pkt_done (g_rx_pkt_done ),
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.pkt_len (),
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.pkt_len (g_rx_pkt_len ),
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.pkt_status (),
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.pkt_status (g_rx_pkt_status ),
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.pkt_drop_ind (),
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.pkt_drop_ind (g_rx_pkt_drop ),
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.pkt_drop_reason ()
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.pkt_drop_reason ()
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);
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);
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|
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| Line 300... |
Line 378... |
.mdio_out_en (mdio_out_en) ,
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.mdio_out_en (mdio_out_en) ,
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.mdio_out (mdio_out),
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.mdio_out (mdio_out),
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.cf_mac_sa (cf_mac_sa),
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.cf_mac_sa (cf_mac_sa),
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.cfg_ip_sa (cfg_ip_sa),
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.cfg_ip_sa (cfg_ip_sa),
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.cfg_mac_filter (cfg_mac_filter)
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.cfg_mac_filter (cfg_mac_filter),
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|
|
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.rx_buf_base_addr (rx_buf_base_addr),
|
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.tx_buf_base_addr (tx_buf_base_addr),
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|
|
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.rx_buf_qbase_addr (rx_buf_qbase_addr),
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.tx_buf_qbase_addr (tx_buf_qbase_addr),
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|
|
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.tx_qcnt_inc (tx_qcnt_inc),
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.tx_qcnt_dec (tx_qcnt_dec),
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.tx_qcnt (tx_qcnt),
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|
|
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.rx_qcnt_inc (rx_qcnt_inc),
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.rx_qcnt_dec (rx_qcnt_dec),
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.rx_qcnt (rx_qcnt)
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|
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);
|
);
|
|
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assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
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assign tx_fifo_rdy = (tx_fifo_aval > 8) ; // Dinesh-A Change it to config
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| Line 336... |
Line 428... |
.wr_total_free_space (),
|
.wr_total_free_space (),
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|
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.rd_clk (app_clk),
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.rd_clk (app_clk),
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.rd_reset_n (app_reset_n),
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.rd_reset_n (app_reset_n),
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.rd_en (app_rxfifo_rden_i),
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.rd_en (app_rxfifo_rden_i),
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.empty (app_rxfifo_empty_o), // sync'ed to rd_clk
|
.empty (app_rxfifo_empty), // sync'ed to rd_clk
|
.aempty (app_rxfifo_aempty_o), // sync'ed to rd_clk
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.aempty (app_rxfifo_aempty_o), // sync'ed to rd_clk
|
.rd_total_aval (app_rxfifo_cnt_o),
|
.rd_total_aval (app_rxfifo_cnt_o),
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.rd_data (app_rxfifo_rdata_o)
|
.rd_data (app_rxfifo_rdata_o)
|
);
|
);
|
|
|
