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https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
[/] [turbo8051/] [trunk/] [rtl/] [lib/] [async_fifo.v] - Diff between revs 67 and 76
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Rev 76 |
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Line 12... |
//// nothing ////
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//// nothing ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// - Dinesh Annayya, dinesha@opencores.org ////
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//// ////
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//// ////
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//// Revision : Mar 2, 2011 ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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// 1. At write clock domain:
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// 1. At write clock domain:
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// wr_total_free_space --> Indicate total free transfer available
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// wr_total_free_space --> Indicate total free transfer available
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// 2. At read clock domain:
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// 2. At read clock domain:
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// rd_total_aval --> Indicate total no of transfer available
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// rd_total_aval --> Indicate total no of transfer available
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//-----------------------------------------------
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//-----------------------------------------------
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`timescale 1ns/1ps
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module async_fifo (wr_clk,
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module async_fifo (wr_clk,
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wr_reset_n,
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wr_reset_n,
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wr_en,
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wr_en,
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wr_data,
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wr_data,
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