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[/] [turbo8051/] [trunk/] [rtl/] [lib/] [async_fifo.v] - Diff between revs 20 and 57
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| Rev 20 |
Rev 57 |
| Line 48... |
Line 48... |
// 1. At write clock domain:
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// 1. At write clock domain:
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// wr_total_free_space --> Indicate total free transfer available
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// wr_total_free_space --> Indicate total free transfer available
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// 2. At read clock domain:
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// 2. At read clock domain:
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// rd_total_aval --> Indicate total no of transfer available
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// rd_total_aval --> Indicate total no of transfer available
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//-----------------------------------------------
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//-----------------------------------------------
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`timescale 1ns/1ps
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module async_fifo (wr_clk,
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module async_fifo (wr_clk,
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wr_reset_n,
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wr_reset_n,
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wr_en,
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wr_en,
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wr_data,
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wr_data,
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