OpenCores
URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [rtl/] [lib/] [async_fifo.v] - Diff between revs 67 and 76

Show entire file | Details | Blame | View Log

Rev 67 Rev 76
Line 12... Line 12...
////    nothing                                                   ////
////    nothing                                                   ////
////                                                              ////
////                                                              ////
////  Author(s):                                                  ////
////  Author(s):                                                  ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////      - Dinesh Annayya, dinesha@opencores.org                 ////
////                                                              ////
////                                                              ////
 
////  Revision : Mar 2, 2011                                      //// 
 
////                                                              ////
//////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
////                                                              ////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// This source file may be used and distributed without         ////
Line 47... Line 49...
//        1. At write clock domain:
//        1. At write clock domain:
//           wr_total_free_space -->  Indicate total free transfer available 
//           wr_total_free_space -->  Indicate total free transfer available 
//        2. At read clock domain:
//        2. At read clock domain:
//           rd_total_aval       -->  Indicate total no of transfer available
//           rd_total_aval       -->  Indicate total no of transfer available
//-----------------------------------------------
//-----------------------------------------------
`timescale  1ns/1ps
 
 
 
module async_fifo (wr_clk,
module async_fifo (wr_clk,
                   wr_reset_n,
                   wr_reset_n,
                   wr_en,
                   wr_en,
                   wr_data,
                   wr_data,

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.