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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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module dpath_ctrl (
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module g_dpath_ctrl (
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rst_n ,
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rst_n ,
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clk ,
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clk ,
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rx_buf_base_addr ,
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tx_buf_base_addr ,
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// gmac core to memory write interface
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// gmac core to memory write interface
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g_rx_mem_rd ,
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g_rx_mem_rd ,
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g_rx_mem_eop ,
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g_rx_mem_eop ,
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g_rx_mem_addr ,
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g_rx_mem_addr ,
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g_rx_block_rxrd ,
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// descr handshake
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g_rx_desc_req ,
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g_rx_desc_discard ,
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g_rx_desc_data ,
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g_rx_desc_ack ,
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g_rx_pkt_done ,
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g_rx_pkt_len ,
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g_rx_pkt_status ,
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g_rx_pkt_drop
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// Memory to gmac core interface
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g_tx_mem_wr ,
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g_tx_mem_eop ,
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g_tx_mem_addr ,
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g_tx_mem_req ,
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g_tx_mem_req_length ,
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g_tx_mem_ack
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);
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);
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input rst_n ;
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input rst_n ;
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input clk ;
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input clk ;
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input [3:0] rx_buf_base_addr ; // 8K Rx Base Address
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input [3:0] tx_buf_base_addr ; // 8K tx Base Address
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// gmac core to memory write interface
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// gmac core to memory write interface
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input g_rx_mem_rd ;
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input g_rx_mem_rd ;
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input g_rx_mem_eop ;
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input g_rx_mem_eop ;
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output [15:0] g_rx_mem_addr ;
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output [15:0] g_rx_mem_addr ;
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output g_rx_block_rxrd ; // Block Rx Read between EOP and PktDone
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input g_rx_pkt_done ; // End of current Packet
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input [11:0] g_rx_pkt_len ; // Packet Length
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input [15:0] g_rx_pkt_status ; // Packet Status
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input g_rx_pkt_drop ; // Packet drop and rewind the pointer
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//-----------------------------------
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// Descriptor handshake
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//----------------------------------
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output g_rx_desc_req ; // rx desc request
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output g_rx_desc_discard ; // rx desc discard indication
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output [31:0] g_rx_desc_data ; // rx desc data
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input g_rx_desc_ack ; // rx desc ack
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// Memory to gmac core interface
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reg g_rx_desc_req ;
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input g_tx_mem_wr ;
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reg g_rx_desc_discard ; // rx desc discard indication
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output g_tx_mem_eop ;
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reg [31:0] g_rx_desc_data ; // rx desc data
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output [15:0] g_tx_mem_addr ;
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output g_tx_mem_req ;
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output [15:0] g_tx_mem_req_length ;
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input g_tx_mem_ack ;
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reg [15:0] g_rx_mem_addr ;
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reg [15:0] g_tx_mem_addr ;
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reg [15:0] g_tx_mem_req_length ;
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reg [15:0] rx_plen ;
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reg [15:0] tx_plen ;
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reg g_tx_mem_req ;
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wire g_tx_mem_eop = ((tx_plen +1) == g_tx_mem_req_length) ? 1'b1 : 1'b0;
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reg [11:0] g_rx_mem_addr_int ;
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wire [15:0] g_rx_mem_addr = {rx_buf_base_addr,g_rx_mem_addr_int[11:0]};
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reg bStartFlag; // Indicate a SOP transaction, used for registering Start Address
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reg g_rx_block_rxrd; // Block Rx Read at the end of EOP and Enable on Packet Done
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reg [11:0] g_rx_saddr;
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always @(negedge rst_n or posedge clk) begin
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always @(negedge rst_n or posedge clk) begin
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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g_rx_mem_addr <= 0;
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g_rx_mem_addr_int <= 0;
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g_tx_mem_addr <= 0;
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bStartFlag <= 1;
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rx_plen <= 0;
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g_rx_block_rxrd <= 0;
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tx_plen <= 0;
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g_rx_saddr <= 0;
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g_rx_desc_discard <= 0;
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g_rx_desc_data <= 0;
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g_rx_desc_req <= 0;
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end
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end
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else begin
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else begin
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if(bStartFlag && g_rx_mem_rd) begin
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g_rx_saddr <= g_rx_mem_addr_int[11:0];
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bStartFlag <= 0;
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end else if (g_rx_mem_rd && g_rx_mem_eop) begin
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bStartFlag <= 1;
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end
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if(g_rx_mem_rd && g_rx_mem_eop)
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g_rx_block_rxrd <= 1;
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else if(g_rx_pkt_done)
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g_rx_block_rxrd <= 0;
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//-----------------------------
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//-----------------------------
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// Finding the Frame Size
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// Finding the Frame Size
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//----------------------------
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//----------------------------
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if(g_rx_mem_rd) begin
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if(g_rx_pkt_done && g_rx_pkt_drop) begin
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g_rx_mem_addr <= g_rx_mem_addr+1;
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g_rx_mem_addr_int <= g_rx_saddr;
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if(g_rx_mem_eop) rx_plen <= 0;
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end else if(g_rx_mem_rd && g_rx_mem_eop) begin
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else rx_plen <= rx_plen +1;
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// Realign to 32 bit boundary and add one free space at eop
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end
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g_rx_mem_addr_int <= g_rx_mem_addr_int+4-g_rx_mem_addr_int[1:0];
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//------------------------
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end else if(g_rx_mem_rd ) begin
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// Generate Tx Request at last transfer of RX Req
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g_rx_mem_addr_int <= g_rx_mem_addr_int+1;
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//------------------------
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end
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//
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// Descriptor Request Generation
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if(g_rx_mem_eop && g_rx_mem_rd) begin
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if(g_rx_pkt_done) begin
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g_tx_mem_req_length <= rx_plen+1;
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g_rx_desc_req <= 1;
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g_tx_mem_req <= 1;
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if(g_rx_pkt_drop) begin
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end else if (g_tx_mem_ack) begin
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g_rx_desc_discard <= 1;
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g_tx_mem_req <= 0;
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end
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//------------------------
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// Generate of EOP for TX Interface at last transfer
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//-------------------------
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if(g_tx_mem_wr) begin
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g_tx_mem_addr <= g_tx_mem_addr+1;
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if(g_tx_mem_req_length == (tx_plen +1)) begin
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tx_plen <= 0;
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end else begin
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end else begin
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tx_plen <= tx_plen +1;
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g_rx_desc_discard <= 0;
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g_rx_desc_data <= {g_rx_pkt_status[5:0],rx_buf_base_addr[3:0],
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g_rx_saddr[11:2],g_rx_pkt_len[11:0]};
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end
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end
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end
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else if (g_rx_desc_ack) begin
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g_rx_desc_req <= 0;
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g_rx_desc_discard <= 0;
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end
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end
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end
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end
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end
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end
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