URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
[/] [turbo8051/] [trunk/] [rtl/] [lib/] [registers.v] - Diff between revs 11 and 76
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 11 |
Rev 76 |
Line 12... |
Line 12... |
//// nothing ////
|
//// nothing ////
|
//// ////
|
//// ////
|
//// Author(s): ////
|
//// Author(s): ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// - Dinesh Annayya, dinesha@opencores.org ////
|
//// ////
|
//// ////
|
|
//// Revision : Mar 2, 2011 ////
|
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
|
//// ////
|
//// ////
|
//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
Line 38... |
Line 40... |
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// from http://www.opencores.org/lgpl.shtml ////
|
//// ////
|
//// ////
|
//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//`timescale 1ns/100ps
|
|
|
|
/*********************************************************************
|
/*********************************************************************
|
** module: bit register
|
** module: bit register
|
|
|
** description: infers a register, make it modular
|
** description: infers a register, make it modular
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.