| Line 59... |
Line 59... |
(
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(
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// Clock and Reset Signals
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// Clock and Reset Signals
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sys_clk,
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sys_clk,
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s_reset_n,
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s_reset_n,
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count_trigger,
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count_inc,
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count_dec,
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reg_sel,
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reg_sel,
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reg_wr_data,
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reg_wr_data,
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reg_wr,
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reg_wr,
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Line 78... |
//-------------------- Parameters -------------------------------------
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//-------------------- Parameters -------------------------------------
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// ------------------- Clock and Reset Signals ------------------------
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// ------------------- Clock and Reset Signals ------------------------
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input sys_clk;
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input sys_clk;
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input s_reset_n;
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input s_reset_n;
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input count_trigger;
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input count_inc; // Counter Increment
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input count_dec; // counter decrement, assuption does not under flow
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input reg_sel;
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input reg_sel;
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input reg_wr;
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input reg_wr;
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input [CWD-1:0] reg_wr_data;
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input [CWD-1:0] reg_wr_data;
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output cntr_intr;
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output cntr_intr;
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output [CWD-1:0] cntrout;
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output [CWD-1:0] cntrout;
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Line 103... |
else begin
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else begin
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if (reg_sel && reg_wr) begin
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if (reg_sel && reg_wr) begin
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reg_trig_cntr <= reg_wr_data;
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reg_trig_cntr <= reg_wr_data;
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end
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end
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else begin
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else begin
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if (count_trigger)
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if (count_inc && count_dec)
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reg_trig_cntr <= reg_trig_cntr;
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else if (count_inc)
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reg_trig_cntr <= reg_trig_cntr + 1'b1;
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reg_trig_cntr <= reg_trig_cntr + 1'b1;
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else if (count_dec)
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reg_trig_cntr <= reg_trig_cntr - 1'b1;
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else
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else
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reg_trig_cntr <= reg_trig_cntr;
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reg_trig_cntr <= reg_trig_cntr;
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end
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end
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end
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end
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end
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end
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assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_trigger) ;
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// only increment overflow is assumed
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// decrement underflow is not handled
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assign cntr_intr = ((reg_trig_cntr + 1) == 'h0 && count_inc) ;
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assign cntrout = reg_trig_cntr;
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assign cntrout = reg_trig_cntr;
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endmodule // must_stat_counter
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endmodule // must_stat_counter
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No newline at end of file
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No newline at end of file
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