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[/] [turbo8051/] [trunk/] [rtl/] [lib/] [wb_rd_mem2mem.v] - Diff between revs 20 and 24
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| Rev 20 |
Rev 24 |
| Line 194... |
Line 194... |
reg [BE_WD-1:0] wbo_be ;
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reg [BE_WD-1:0] wbo_be ;
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reg wbo_cyc ;
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reg wbo_cyc ;
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reg mem_ack ;
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reg mem_ack ;
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wire mem_wr = wbo_ack;
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wire mem_wr = wbo_ack;
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// Generate Next Address, to fix the read to address inc issue
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wire [15:0] taddr = mem_addr+1;
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wire [7:0] mem_din = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
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wire [7:0] mem_din = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
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(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
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(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
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(mem_addr[1:0] == 2'b10) ? wbo_dout[23:16] : wbo_dout[31:24] ;
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(mem_addr[1:0] == 2'b10) ? wbo_dout[23:16] : wbo_dout[31:24] ;
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| Line 220... |
Line 222... |
cnt <= mem_txfr;
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cnt <= mem_txfr;
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wbo_taddr <= mem_taddr;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= mem_addr[14:2];
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wbo_stb <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_we <= 1'b0;
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wbo_we <= 1'b0;
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wbo_be <= {BE_WD{1'b1}};
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wbo_be <= 1 << mem_addr[1:0];
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wbo_cyc <= 1'b1;
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wbo_cyc <= 1'b1;
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mem_ack <= 1;
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mem_ack <= 1;
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state <= TXFR;
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state <= TXFR;
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end
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end
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end
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end
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TXFR: begin
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TXFR: begin
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mem_ack <= 0;
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mem_ack <= 0;
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if(wbo_ack) begin
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if(wbo_ack) begin
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cnt <= cnt-1;
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cnt <= cnt-1;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= taddr[14:2];
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wbo_be <= 1 << taddr[1:0];
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if(cnt == 1) begin
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if(cnt == 1) begin
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wbo_stb <= 1'b0;
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wbo_stb <= 1'b0;
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wbo_cyc <= 1'b0;
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wbo_cyc <= 1'b0;
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state <= IDLE;
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state <= IDLE;
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end
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end
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