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Line 41... |
//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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/**********************************************
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/**********************************************
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Web-bone , Read from Wishbone Memory and Write to internal Memory
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Web-bone , Read from Wishbone Memory and Write to internal Memory
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This block handles following task
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1. Check the Descriptor Q for not empty
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2. If the Descriptor Q is not empty, the read the 32 bit descriptor
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3. The 32 bit descriptor holds following information
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[11:0] - Packet Length
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[25:12] - MSB [15:2] of Packet Start Location
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[31:26] - Packet Status
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4. Based on the Packet Length, Read the data from external Data memory
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and write it to Internal Memory
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**********************************************/
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**********************************************/
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module wb_rd_mem2mem (
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module wb_rd_mem2mem (
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rst_n ,
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rst_n ,
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clk ,
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clk ,
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// descriptor handshake
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cfg_desc_baddr ,
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desc_q_empty ,
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// Master Interface Signal
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// Master Interface Signal
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mem_req ,
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mem_txfr ,
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mem_ack ,
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mem_taddr ,
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mem_taddr ,
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mem_addr ,
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mem_full ,
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mem_full ,
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mem_afull ,
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mem_afull ,
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mem_wr ,
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mem_wr ,
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mem_din ,
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mem_din ,
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//---------------------
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//---------------------
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// State Machine Parameter
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// State Machine Parameter
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//--------------------
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//--------------------
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parameter IDLE = 0;
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parameter IDLE = 0;
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parameter TXFR = 1;
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parameter DESC_RD = 1;
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parameter DATA_WAIT = 2;
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parameter TXFR = 3;
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//-------------------------------------------
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//-------------------------------------------
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// Input Declaration
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// Input Declaration
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//------------------------------------------
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//------------------------------------------
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// rising edge of [CLK_I].
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// rising edge of [CLK_I].
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input rst_n ; // RST_I The reset input [RST_I] forces the WISHBONE interface
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input rst_n ; // RST_I The reset input [RST_I] forces the WISHBONE interface
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// to restart. Furthermore, all internal self-starting state
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// to restart. Furthermore, all internal self-starting state
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// machines will be forced into an initial state.
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// machines will be forced into an initial state.
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//---------------------------------
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// Descriptor Interface
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//---------------------------------
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input [15:6] cfg_desc_baddr ; // descriptor Base Address
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input desc_q_empty ;
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//------------------------------------------
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//------------------------------------------
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// Stanard Memory Interface
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// Stanard Memory Interface
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//------------------------------------------
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//------------------------------------------
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input mem_req ;
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input [15:0] mem_txfr ;
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output mem_ack ;
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input [TAR_WD-1:0] mem_taddr ; // target address
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input [TAR_WD-1:0] mem_taddr ; // target address
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input [15:0] mem_addr ; // memory address
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input mem_full ; // memory full
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input mem_full ; // memory full
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input mem_afull ; // memory afull
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input mem_afull ; // memory afull
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output mem_wr ; // memory read
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output mem_wr ; // memory Write
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output [7:0] mem_din ; // memory read data
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output [8:0] mem_din ; // memory read data
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//------------------------------------------
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//------------------------------------------
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// External Memory WB Interface
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// External Memory WB Interface
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//------------------------------------------
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//------------------------------------------
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output wbo_stb ; // STB_O The strobe output [STB_O] indicates a valid data
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output wbo_stb ; // STB_O The strobe output [STB_O] indicates a valid data
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Line 197... |
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//----------------------------------------
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//----------------------------------------
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// Register Declration
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// Register Declration
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//----------------------------------------
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//----------------------------------------
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reg state ;
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reg [1:0] state ;
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reg [15:0] cnt ;
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reg [15:0] cnt ;
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reg [TAR_WD-1:0] wbo_taddr ;
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reg [TAR_WD-1:0] wbo_taddr ;
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reg [ADR_WD-1:0] wbo_addr ;
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reg [ADR_WD-1:0] wbo_addr ;
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reg wbo_stb ;
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reg wbo_stb ;
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reg wbo_we ;
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reg wbo_we ;
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reg [BE_WD-1:0] wbo_be ;
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reg [BE_WD-1:0] wbo_be ;
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reg wbo_cyc ;
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reg wbo_cyc ;
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reg mem_ack ;
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reg [15:0] mem_addr ;
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wire mem_wr = (state == TXFR) ? wbo_ack: 1'b0 ;
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wire mem_wr = wbo_ack;
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// Generate Next Address, to fix the read to address inc issue
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// Generate Next Address, to fix the read to address inc issue
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wire [15:0] taddr = mem_addr+1;
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wire [15:0] taddr = mem_addr+1;
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wire [7:0] mem_din = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
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assign mem_din[7:0] = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
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(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
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(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
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(mem_addr[1:0] == 2'b10) ? wbo_dout[23:16] : wbo_dout[31:24] ;
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(mem_addr[1:0] == 2'b10) ? wbo_dout[23:16] : wbo_dout[31:24] ;
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assign mem_din[8] = (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
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reg [3:0] desc_ptr;
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always @(negedge rst_n or posedge clk) begin
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always @(negedge rst_n or posedge clk) begin
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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state <= IDLE;
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state <= IDLE;
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wbo_taddr <= 0;
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wbo_taddr <= 0;
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wbo_addr <= 0;
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wbo_addr <= 0;
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wbo_stb <= 0;
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wbo_stb <= 0;
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wbo_we <= 0;
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wbo_we <= 0;
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wbo_be <= 0;
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wbo_be <= 0;
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wbo_cyc <= 0;
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wbo_cyc <= 0;
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mem_ack <= 0;
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desc_ptr <= 0;
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mem_addr <= 0;
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end
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end
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else begin
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else begin
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case(state)
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case(state)
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IDLE: begin
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IDLE: begin
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if(mem_req && !mem_full) begin
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// Check for Descriptor Q not empty
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cnt <= mem_txfr;
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if(!desc_q_empty) begin
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wbo_taddr <= mem_taddr;
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wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]};
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wbo_be <= 4'hF;
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wbo_we <= 1'b0;
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wbo_stb <= 1'b1;
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wbo_cyc <= 1;
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state <= DESC_RD;
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desc_ptr <= desc_ptr+1;
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end
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end
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DESC_RD: begin
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// wait for web-bone ack
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if(wbo_ack) begin
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wbo_cyc <= 1'b0;
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wbo_stb <= 1'b0;
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state <= IDLE;
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cnt <= wbo_dout[11:0];
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mem_addr <= {wbo_dout[27:12],2'b0};
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state <= DATA_WAIT;
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end
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end
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DATA_WAIT: begin
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// check for internal memory not full and initiate
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// the transfer
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if(!mem_full) begin
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wbo_taddr <= mem_taddr;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= mem_addr[14:2];
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wbo_stb <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_we <= 1'b0;
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wbo_we <= 1'b0;
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wbo_be <= 1 << mem_addr[1:0];
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wbo_be <= 4'hF;
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wbo_cyc <= 1'b1;
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wbo_cyc <= 1'b1;
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mem_ack <= 1;
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state <= TXFR;
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state <= TXFR;
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end
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end
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end
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end
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TXFR: begin
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TXFR: begin
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mem_ack <= 0;
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if(wbo_ack) begin
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if(wbo_ack) begin
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mem_addr <= mem_addr+1;
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cnt <= cnt-1;
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cnt <= cnt-1;
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wbo_addr <= taddr[14:2];
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wbo_addr <= taddr[14:2];
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wbo_be <= 1 << taddr[1:0];
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wbo_be <= 4'hF;
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if(cnt == 1) begin
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if(cnt == 1) begin
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wbo_stb <= 1'b0;
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wbo_stb <= 1'b0;
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wbo_cyc <= 1'b0;
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wbo_cyc <= 1'b0;
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state <= IDLE;
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state <= IDLE;
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end
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end
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else if(mem_afull) begin
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else if(mem_afull) begin // to handle the interburst fifo full case
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wbo_cyc <= 1'b0;
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wbo_stb <= 1'b0;
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wbo_stb <= 1'b0;
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end
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end
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end else if(!mem_full) begin
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end else if(!mem_full) begin // to handle interbust fifo full cases
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wbo_cyc <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_stb <= 1'b1;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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