| Line 97... |
Line 97... |
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parameter IDLE = 0;
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parameter IDLE = 0;
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parameter DESC_RD = 1;
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parameter DESC_RD = 1;
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parameter DATA_WAIT = 2;
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parameter DATA_WAIT = 2;
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parameter TXFR = 3;
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parameter TXFR = 3;
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parameter MEM_WRITE2 = 4;
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parameter MEM_WRITE3 = 5;
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parameter MEM_WRITE4 = 6;
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//-------------------------------------------
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//-------------------------------------------
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// Input Declaration
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// Input Declaration
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//------------------------------------------
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//------------------------------------------
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| Line 197... |
Line 200... |
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//----------------------------------------
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//----------------------------------------
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// Register Declration
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// Register Declration
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//----------------------------------------
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//----------------------------------------
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reg [1:0] state ;
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reg [2:0] state ;
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reg [15:0] cnt ;
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reg [15:0] cnt ;
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reg [TAR_WD-1:0] wbo_taddr ;
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reg [TAR_WD-1:0] wbo_taddr ;
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reg [ADR_WD-1:0] wbo_addr ;
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reg [ADR_WD-1:0] wbo_addr ;
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reg wbo_stb ;
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reg wbo_stb ;
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reg wbo_we ;
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reg wbo_we ;
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reg [BE_WD-1:0] wbo_be ;
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reg [BE_WD-1:0] wbo_be ;
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reg wbo_cyc ;
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reg wbo_cyc ;
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reg [15:0] mem_addr ;
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reg [15:0] mem_addr ;
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wire mem_wr = (state == TXFR) ? wbo_ack: 1'b0 ;
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// Generate Next Address, to fix the read to address inc issue
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wire [15:0] taddr = mem_addr+1;
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assign mem_din[7:0] = (mem_addr[1:0] == 2'b00) ? wbo_dout[7:0] :
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(mem_addr[1:0] == 2'b01) ? wbo_dout[15:8] :
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(mem_addr[1:0] == 2'b10) ? wbo_dout[23:16] : wbo_dout[31:24] ;
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assign mem_din[8] = (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
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reg [3:0] desc_ptr;
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reg [3:0] desc_ptr;
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reg [23:0] tWrData; // Temp Write Data
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reg [8:0] mem_din;
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reg mem_wr;
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always @(negedge rst_n or posedge clk) begin
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always @(negedge rst_n or posedge clk) begin
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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state <= IDLE;
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state <= IDLE;
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wbo_taddr <= 0;
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wbo_taddr <= 0;
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| Line 231... |
Line 229... |
wbo_we <= 0;
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wbo_we <= 0;
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wbo_be <= 0;
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wbo_be <= 0;
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wbo_cyc <= 0;
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wbo_cyc <= 0;
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desc_ptr <= 0;
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desc_ptr <= 0;
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mem_addr <= 0;
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mem_addr <= 0;
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mem_din <= 0;
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tWrData <= 0;
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mem_wr <= 0;
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end
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end
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else begin
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else begin
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case(state)
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case(state)
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IDLE: begin
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IDLE: begin
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mem_wr <= 0;
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// Check for Descriptor Q not empty
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// Check for Descriptor Q not empty
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if(!desc_q_empty) begin
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if(!desc_q_empty) begin
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wbo_taddr <= mem_taddr;
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wbo_taddr <= mem_taddr;
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wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]};
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wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]};
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wbo_be <= 4'hF;
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wbo_be <= 4'hF;
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| Line 260... |
Line 262... |
state <= DATA_WAIT;
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state <= DATA_WAIT;
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end
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end
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end
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end
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DATA_WAIT: begin
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DATA_WAIT: begin
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mem_wr <= 0; // Reset the write for handling interburst
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// check for internal memory not full and initiate
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// check for internal memory not full and initiate
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// the transfer
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// the transfer
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if(!mem_full) begin
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if(!(mem_full || mem_afull)) begin
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wbo_taddr <= mem_taddr;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= mem_addr[14:2];
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wbo_stb <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_we <= 1'b0;
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wbo_we <= 1'b0;
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wbo_be <= 4'hF;
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wbo_be <= 4'hF;
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| Line 274... |
Line 277... |
state <= TXFR;
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state <= TXFR;
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end
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end
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end
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end
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TXFR: begin
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TXFR: begin
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if(wbo_ack) begin
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if(wbo_ack) begin
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mem_addr <= mem_addr+1;
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wbo_cyc <= 1'b0;
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wbo_stb <= 1'b0;
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mem_addr <= mem_addr+4;
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mem_din[7:0] <= wbo_dout[7:0]; // Write First Byte
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tWrData <= wbo_dout[31:8];
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mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
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mem_wr <= 1;
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cnt <= cnt-1;
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cnt <= cnt-1;
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wbo_addr <= taddr[14:2];
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wbo_be <= 4'hF;
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if(cnt == 1) begin
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if(cnt == 1) begin
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wbo_stb <= 1'b0;
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wbo_cyc <= 1'b0;
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state <= IDLE;
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state <= IDLE;
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end else begin
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state <= MEM_WRITE2;
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end
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end
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else if(mem_afull) begin // to handle the interburst fifo full case
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wbo_cyc <= 1'b0;
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wbo_stb <= 1'b0;
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end
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end
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end else if(!mem_full) begin // to handle interbust fifo full cases
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end
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wbo_cyc <= 1'b1;
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MEM_WRITE2: begin // Write 2nd Byte
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wbo_stb <= 1'b1;
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if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
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mem_din[7:0] <= tWrData[7:0];
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mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
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mem_wr <= 1;
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cnt <= cnt-1;
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if(cnt == 1) begin
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state <= IDLE;
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end else begin
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state <= MEM_WRITE3;
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end
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end else begin
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mem_wr <= 0;
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end
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end
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MEM_WRITE3: begin // Write 3rd Byte
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if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
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mem_din[7:0] <= tWrData[15:8];
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mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
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mem_wr <= 1;
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cnt <= cnt-1;
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if(cnt == 1) begin
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state <= IDLE;
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end else begin
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state <= MEM_WRITE4;
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end
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end else begin
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mem_wr <= 0;
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end
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end
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MEM_WRITE4: begin // Write 4th Byte
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if(!(mem_full || mem_afull)) begin // to handle the interburst fifo full case
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mem_din[7:0] <= tWrData[23:16];
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mem_din[8] <= (cnt == 1) ? 1'b1 : 1'b0; // EOP generation at last transfer
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mem_wr <= 1;
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cnt <= cnt-1;
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if(cnt == 1) begin
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state <= IDLE;
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end else begin
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state <= DATA_WAIT;
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end
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end else begin
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mem_wr <= 0;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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