URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
[/] [turbo8051/] [trunk/] [rtl/] [lib/] [wb_wr_mem2mem.v] - Diff between revs 20 and 24
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 20 |
Rev 24 |
| Line 177... |
Line 177... |
reg [BE_WD-1:0] wbo_be ;
|
reg [BE_WD-1:0] wbo_be ;
|
reg wbo_cyc ;
|
reg wbo_cyc ;
|
reg [D_WD-1:0] wbo_din ;
|
reg [D_WD-1:0] wbo_din ;
|
reg state ;
|
reg state ;
|
|
|
wire mem_rd = wbo_ack;
|
reg mem_rd ;
|
|
|
|
|
always @(negedge rst_n or posedge clk) begin
|
always @(negedge rst_n or posedge clk) begin
|
if(rst_n == 0) begin
|
if(rst_n == 0) begin
|
wbo_taddr <= 0;
|
wbo_taddr <= 0;
|
wbo_addr <= 0;
|
wbo_addr <= 0;
|
wbo_stb <= 0;
|
wbo_stb <= 0;
|
wbo_we <= 0;
|
wbo_we <= 0;
|
wbo_be <= 0;
|
wbo_be <= 0;
|
wbo_cyc <= 0;
|
wbo_cyc <= 0;
|
wbo_din <= 0;
|
wbo_din <= 0;
|
|
mem_rd <= 0;
|
state <= IDLE;
|
state <= IDLE;
|
end
|
end
|
else begin
|
else begin
|
case(state)
|
case(state)
|
IDLE: begin
|
IDLE: begin
|
| Line 201... |
Line 203... |
wbo_stb <= 1'b1;
|
wbo_stb <= 1'b1;
|
wbo_we <= 1'b1;
|
wbo_we <= 1'b1;
|
wbo_be <= 1 << mem_addr[1:0];
|
wbo_be <= 1 << mem_addr[1:0];
|
wbo_cyc <= 1;
|
wbo_cyc <= 1;
|
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
|
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
|
|
mem_rd <= 1;
|
state <= XFR;
|
state <= XFR;
|
end
|
end
|
end
|
end
|
XFR: begin
|
XFR: begin
|
if(wbo_ack) begin
|
if(wbo_ack) begin
|
wbo_addr <= mem_taddr;
|
wbo_addr <= mem_addr[14:2];
|
wbo_be <= 1 << mem_addr[1:0];
|
wbo_be <= 1 << mem_addr[1:0];
|
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
|
wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
|
if(mem_aempty) begin
|
if(mem_aempty || mem_empty) begin
|
wbo_stb <= 1'b0;
|
wbo_stb <= 1'b0;
|
wbo_cyc <= 0;
|
wbo_cyc <= 0;
|
state <= IDLE;
|
state <= IDLE;
|
|
end else begin
|
|
mem_rd <= 1;
|
end
|
end
|
|
end else begin
|
|
mem_rd <= 0;
|
end
|
end
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
end
|
end
|
© copyright 1999-2025
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.