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[/] [turbo8051/] [trunk/] [rtl/] [lib/] [wb_wr_mem2mem.v] - Diff between revs 20 and 24
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| Rev 20 |
Rev 24 |
| Line 177... |
Line 177... |
reg [BE_WD-1:0] wbo_be ;
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reg [BE_WD-1:0] wbo_be ;
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reg wbo_cyc ;
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reg wbo_cyc ;
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reg [D_WD-1:0] wbo_din ;
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reg [D_WD-1:0] wbo_din ;
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reg state ;
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reg state ;
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wire mem_rd = wbo_ack;
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reg mem_rd ;
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always @(negedge rst_n or posedge clk) begin
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always @(negedge rst_n or posedge clk) begin
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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wbo_taddr <= 0;
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wbo_taddr <= 0;
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wbo_addr <= 0;
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wbo_addr <= 0;
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wbo_stb <= 0;
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wbo_stb <= 0;
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wbo_we <= 0;
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wbo_we <= 0;
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wbo_be <= 0;
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wbo_be <= 0;
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wbo_cyc <= 0;
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wbo_cyc <= 0;
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wbo_din <= 0;
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wbo_din <= 0;
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mem_rd <= 0;
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state <= IDLE;
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state <= IDLE;
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end
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end
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else begin
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else begin
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case(state)
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case(state)
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IDLE: begin
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IDLE: begin
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| Line 201... |
Line 203... |
wbo_stb <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_we <= 1'b1;
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wbo_we <= 1'b1;
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wbo_be <= 1 << mem_addr[1:0];
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wbo_be <= 1 << mem_addr[1:0];
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wbo_cyc <= 1;
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wbo_cyc <= 1;
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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mem_rd <= 1;
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state <= XFR;
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state <= XFR;
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end
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end
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end
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end
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XFR: begin
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XFR: begin
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if(wbo_ack) begin
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if(wbo_ack) begin
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wbo_addr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_be <= 1 << mem_addr[1:0];
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wbo_be <= 1 << mem_addr[1:0];
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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if(mem_aempty) begin
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if(mem_aempty || mem_empty) begin
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wbo_stb <= 1'b0;
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wbo_stb <= 1'b0;
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wbo_cyc <= 0;
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wbo_cyc <= 0;
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state <= IDLE;
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state <= IDLE;
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end else begin
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mem_rd <= 1;
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end
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end
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end else begin
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mem_rd <= 0;
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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