| Line 56... |
Line 56... |
mem_addr ,
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mem_addr ,
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mem_empty ,
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mem_empty ,
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mem_aempty ,
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mem_aempty ,
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mem_rd ,
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mem_rd ,
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mem_dout ,
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mem_dout ,
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mem_eop ,
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cfg_desc_baddr ,
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desc_req ,
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desc_ack ,
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desc_disccard ,
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desc_data ,
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// Slave Interface Signal
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// Slave Interface Signal
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wbo_din ,
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wbo_din ,
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wbo_taddr ,
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wbo_taddr ,
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wbo_addr ,
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wbo_addr ,
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| Line 77... |
Line 85... |
parameter BE_WD = 2; // Byte Enable
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parameter BE_WD = 2; // Byte Enable
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parameter ADR_WD = 28; // Address Width
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parameter ADR_WD = 28; // Address Width
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parameter TAR_WD = 4; // Target Width
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parameter TAR_WD = 4; // Target Width
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// State Machine
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// State Machine
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parameter IDLE = 0;
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parameter IDLE = 2'h0;
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parameter XFR = 1;
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parameter XFR = 2'h1;
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parameter DESC_WAIT = 2'h2;
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parameter DESC_XFR = 2'h3;
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input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
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input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
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// for the internal logic within the WISHBONE interconnect.
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// for the internal logic within the WISHBONE interconnect.
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// All WISHBONE output signals are registered at the
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// All WISHBONE output signals are registered at the
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// rising edge of [CLK_I].
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// rising edge of [CLK_I].
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| Line 99... |
Line 109... |
input [15:0] mem_addr; // memory address
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input [15:0] mem_addr; // memory address
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input mem_empty; // memory empty
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input mem_empty; // memory empty
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input mem_aempty; // memory empty
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input mem_aempty; // memory empty
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output mem_rd; // memory read
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output mem_rd; // memory read
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input [7:0] mem_dout; // memory read data
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input [7:0] mem_dout; // memory read data
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input mem_eop; // Last Transfer indication
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//----------------------------------------
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// Discriptor defination
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//----------------------------------------
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input desc_req; // descriptor request
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output desc_ack; // descriptor ack
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input desc_disccard;// descriptor discard
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input [15:6] cfg_desc_baddr; // descriptor memory base address
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input [31:0] desc_data; // descriptor data
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//------------------------------------------
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//------------------------------------------
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// External Memory WB Interface
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// External Memory WB Interface
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//------------------------------------------
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//------------------------------------------
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output [TAR_WD-1:0] wbo_taddr ;
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output [TAR_WD-1:0] wbo_taddr ;
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| Line 175... |
Line 195... |
reg wbo_stb ;
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reg wbo_stb ;
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reg wbo_we ;
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reg wbo_we ;
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reg [BE_WD-1:0] wbo_be ;
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reg [BE_WD-1:0] wbo_be ;
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reg wbo_cyc ;
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reg wbo_cyc ;
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reg [D_WD-1:0] wbo_din ;
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reg [D_WD-1:0] wbo_din ;
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reg state ;
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reg [1:0] state ;
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reg mem_rd ;
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reg mem_rd ;
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reg [3:0] desc_ptr ; // descriptor pointer, in 32 bit mode
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reg mem_eop_l ; // delayed eop signal
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reg desc_ack ; // delayed eop signal
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always @(negedge rst_n or posedge clk) begin
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always @(negedge rst_n or posedge clk) begin
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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wbo_taddr <= 0;
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wbo_taddr <= 0;
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wbo_addr <= 0;
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wbo_addr <= 0;
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| Line 190... |
Line 212... |
wbo_we <= 0;
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wbo_we <= 0;
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wbo_be <= 0;
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wbo_be <= 0;
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wbo_cyc <= 0;
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wbo_cyc <= 0;
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wbo_din <= 0;
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wbo_din <= 0;
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mem_rd <= 0;
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mem_rd <= 0;
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desc_ptr <= 0;
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mem_eop_l <= 0;
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desc_ack <= 0;
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state <= IDLE;
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state <= IDLE;
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end
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end
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else begin
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else begin
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case(state)
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case(state)
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IDLE: begin
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IDLE: begin
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desc_ack <= 0;
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if(!mem_empty) begin
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if(!mem_empty) begin
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wbo_taddr <= mem_taddr;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= mem_addr[14:2];
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wbo_stb <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_we <= 1'b1;
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wbo_we <= 1'b1;
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wbo_be <= 1 << mem_addr[1:0];
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wbo_be <= 1 << mem_addr[1:0];
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wbo_cyc <= 1;
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wbo_cyc <= 1;
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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mem_eop_l <= mem_eop;
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mem_rd <= 1;
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mem_rd <= 1;
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state <= XFR;
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state <= XFR;
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end
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end
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end
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end
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XFR: begin
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XFR: begin
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if(wbo_ack) begin
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if(wbo_ack) begin
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mem_eop_l <= mem_eop;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= mem_addr[14:2];
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wbo_be <= 1 << mem_addr[1:0];
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wbo_be <= 1 << mem_addr[1:0];
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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if(mem_aempty || mem_empty) begin
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if(mem_eop_l) begin
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state <= DESC_WAIT;
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end
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else if(mem_aempty || mem_empty) begin
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wbo_stb <= 1'b0;
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wbo_stb <= 1'b0;
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wbo_cyc <= 0;
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wbo_cyc <= 0;
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state <= IDLE;
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state <= IDLE;
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end else begin
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end else begin
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mem_rd <= 1;
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mem_rd <= 1;
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end
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end
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end else begin
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end else begin
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mem_rd <= 0;
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mem_rd <= 0;
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end
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end
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end
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end
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DESC_WAIT: begin
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if(desc_req) begin
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desc_ack <= 1;
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if(desc_disccard) begin // if the Desc is discarded
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state <= IDLE;
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end
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else begin
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wbo_addr <= {cfg_desc_baddr[15:6],desc_ptr[3:0]}; // Each Transfer is 32bit
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wbo_be <= 4'hF;
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wbo_din <= desc_data;
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wbo_we <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_cyc <= 1;
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state <= DESC_XFR;
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desc_ptr <= desc_ptr+1;
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end
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end
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end
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DESC_XFR: begin
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desc_ack <= 0;
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if(wbo_ack) begin
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wbo_stb <= 1'b0;
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wbo_cyc <= 1'b0;
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state <= IDLE;
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end
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end
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endcase
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endcase
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end
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end
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end
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end
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