| Line 85... |
Line 85... |
parameter BE_WD = 2; // Byte Enable
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parameter BE_WD = 2; // Byte Enable
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parameter ADR_WD = 28; // Address Width
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parameter ADR_WD = 28; // Address Width
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parameter TAR_WD = 4; // Target Width
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parameter TAR_WD = 4; // Target Width
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// State Machine
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// State Machine
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parameter IDLE = 2'h0;
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parameter IDLE = 3'h0;
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parameter XFR = 2'h1;
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parameter RD_BYTE1 = 3'h1;
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parameter DESC_WAIT = 2'h2;
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parameter RD_BYTE2 = 3'h2;
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parameter DESC_XFR = 2'h3;
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parameter RD_BYTE3 = 3'h3;
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parameter RD_BYTE4 = 3'h4;
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parameter WB_XFR = 3'h5;
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parameter DESC_WAIT = 3'h6;
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parameter DESC_XFR = 3'h7;
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input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
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input clk ; // CLK_I The clock input [CLK_I] coordinates all activities
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// for the internal logic within the WISHBONE interconnect.
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// for the internal logic within the WISHBONE interconnect.
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// All WISHBONE output signals are registered at the
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// All WISHBONE output signals are registered at the
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// rising edge of [CLK_I].
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// rising edge of [CLK_I].
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| Line 195... |
Line 199... |
reg wbo_stb ;
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reg wbo_stb ;
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reg wbo_we ;
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reg wbo_we ;
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reg [BE_WD-1:0] wbo_be ;
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reg [BE_WD-1:0] wbo_be ;
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reg wbo_cyc ;
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reg wbo_cyc ;
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reg [D_WD-1:0] wbo_din ;
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reg [D_WD-1:0] wbo_din ;
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reg [1:0] state ;
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reg [2:0] state ;
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reg mem_rd ;
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reg mem_rd ;
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reg [3:0] desc_ptr ; // descriptor pointer, in 32 bit mode
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reg [3:0] desc_ptr ; // descriptor pointer, in 32 bit mode
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reg mem_eop_l ; // delayed eop signal
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reg mem_eop_l ; // delayed eop signal
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reg desc_ack ; // delayed eop signal
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reg desc_ack ; // delayed eop signal
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reg [23:0] tWrData; // Temp 24 Bit Data
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always @(negedge rst_n or posedge clk) begin
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always @(negedge rst_n or posedge clk) begin
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if(rst_n == 0) begin
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if(rst_n == 0) begin
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wbo_taddr <= 0;
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wbo_taddr <= 0;
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wbo_addr <= 0;
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wbo_addr <= 0;
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wbo_stb <= 0;
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wbo_stb <= 0;
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| Line 215... |
Line 220... |
wbo_din <= 0;
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wbo_din <= 0;
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mem_rd <= 0;
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mem_rd <= 0;
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desc_ptr <= 0;
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desc_ptr <= 0;
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mem_eop_l <= 0;
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mem_eop_l <= 0;
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desc_ack <= 0;
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desc_ack <= 0;
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tWrData <= 0;
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state <= IDLE;
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state <= IDLE;
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end
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end
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else begin
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else begin
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case(state)
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case(state)
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IDLE: begin
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IDLE: begin
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desc_ack <= 0;
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desc_ack <= 0;
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if(!mem_empty) begin
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if(!mem_empty) begin
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mem_rd <= 1;
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mem_eop_l <= 0;
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tWrData[7:0] <= mem_dout[7:0];
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state <= RD_BYTE1;
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end
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end
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RD_BYTE1: begin // End of First Transfer
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if(mem_rd && mem_eop) begin
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mem_rd <= 0;
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mem_eop_l <= mem_eop;
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wbo_taddr <= mem_taddr;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= mem_addr[14:2];
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wbo_stb <= 1'b1;
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wbo_stb <= 1'b1;
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wbo_we <= 1'b1;
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wbo_we <= 1'b1;
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wbo_be <= 1 << mem_addr[1:0];
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wbo_be <= 4'h1; // Assigned Aligned 32bit address
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wbo_din <= {24'h0,mem_dout[7:0]};
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wbo_cyc <= 1;
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wbo_cyc <= 1;
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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state <= WB_XFR;
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end else if(!(mem_empty || (mem_rd && mem_aempty))) begin
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mem_rd <= 1;
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state <= RD_BYTE2;
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end else begin
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mem_rd <= 0;
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end
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if(mem_rd) begin
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tWrData[7:0] <= mem_dout[7:0];
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end
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end
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RD_BYTE2: begin // End of Second Transfer
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if(mem_rd && mem_eop) begin
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mem_rd <= 0;
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mem_eop_l <= mem_eop;
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mem_eop_l <= mem_eop;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_stb <= 1'b1;
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wbo_we <= 1'b1;
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wbo_be <= 4'h3; // Assigned Aligned 32bit address
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wbo_din <= {16'h0,mem_dout[7:0],tWrData[7:0]};
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wbo_cyc <= 1;
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state <= WB_XFR;
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end else if(!(mem_empty || (mem_rd && mem_aempty))) begin
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mem_rd <= 1;
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mem_rd <= 1;
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state <= XFR;
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state <= RD_BYTE3;
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end else begin
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mem_rd <= 0;
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end
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end
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if(mem_rd) begin
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tWrData[15:8] <= mem_dout[7:0];
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end
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end
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XFR: begin
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end
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if(wbo_ack) begin
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RD_BYTE3: begin // End of Third Transfer
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if(mem_rd && mem_eop) begin
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mem_rd <= 0;
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mem_eop_l <= mem_eop;
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mem_eop_l <= mem_eop;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_addr <= mem_addr[14:2];
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wbo_be <= 1 << mem_addr[1:0];
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wbo_stb <= 1'b1;
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wbo_din <= {mem_dout,mem_dout,mem_dout,mem_dout};
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wbo_we <= 1'b1;
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if(mem_eop_l) begin
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wbo_be <= 4'h7; // Assigned Aligned 32bit address
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state <= DESC_WAIT;
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wbo_din <= {8'h0,mem_dout[7:0],tWrData[15:0]};
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wbo_cyc <= 1;
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state <= WB_XFR;
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end else if(!(mem_empty || (mem_rd && mem_aempty))) begin
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mem_rd <= 1;
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state <= RD_BYTE4;
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end else begin
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mem_rd <= 0;
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end
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if(mem_rd) begin
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tWrData[23:16] <= mem_dout[7:0];
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end
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end
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RD_BYTE4: begin // End of Fourth Transfer
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mem_rd <= 0;
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mem_eop_l <= mem_eop;
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wbo_taddr <= mem_taddr;
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wbo_addr <= mem_addr[14:2];
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wbo_stb <= 1'b1;
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wbo_we <= 1'b1;
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wbo_be <= 4'hF; // Assigned Aligned 32bit address
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wbo_din <= {mem_dout[7:0],tWrData[23:0]};
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wbo_cyc <= 1;
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state <= WB_XFR;
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end
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end
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else if(mem_aempty || mem_empty) begin
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wbo_stb <= 1'b0;
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WB_XFR: begin
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if(wbo_ack) begin
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wbo_stb <= 0;
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wbo_cyc <= 0;
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wbo_cyc <= 0;
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state <= IDLE;
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if(mem_eop_l) begin
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state <= DESC_WAIT;
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end else begin
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end else begin
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mem_rd <= 1;
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state <= IDLE; // Next Byte
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end
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end
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end else begin
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mem_rd <= 0;
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end
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end
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end
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end
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DESC_WAIT: begin
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DESC_WAIT: begin
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if(desc_req) begin
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if(desc_req) begin
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desc_ack <= 1;
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desc_ack <= 1;
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if(desc_disccard) begin // if the Desc is discarded
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if(desc_disccard) begin // if the Desc is discarded
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state <= IDLE;
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state <= IDLE;
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