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URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [log/] [spi_test_1.log] - Diff between revs 74 and 76

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Reading /mtitcl/vsim/pref.tcl
 
Reading D:/Microsemi/Libero_v10.1/Model/tcl/vsim/pref.tcl
 
 
 
 
 
# 10.2b
 
# 10.1b
 
 
 
 
 
# vsim +spi_test_1 -do run.do -c tb_top
 
# vsim +spi_test_1 -do run.do -c tb_top
 
# //  Questa Sim-64
 
# //  ModelSim ACTEL 10.1b Apr 27 2012
 
# //  Version 10.2b linux_x86_64 May 16 2013
 
 
 
# //
 
# //
 
# //  Copyright 1991-2013 Mentor Graphics Corporation
 
# //  Copyright 1991-2012 Mentor Graphics Corporation
 
# //  All Rights Reserved.
 
# //  All Rights Reserved.
 
# //
 
# //
 
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
 
# //  THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
 
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
 
# //  WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
 
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
 
# //  LICENSORS AND IS SUBJECT TO LICENSE TERMS.
 
# //
 
# //
 
# Loading sv_std.std
 
# Loading sv_std.std
 
# Loading work.tb_top(fast)
 
# Loading work.tb_top
 
# Loading work.oc8051_top(fast)
 
# Loading work.digital_core
 
# Loading work.tb_eth_top(fast)
 
# Loading work.clkgen
 
# Loading work.AT45DB321(fast)
 
# Loading work.clk_ctl
 
 
 
# Loading work.wb_crossbar
 
 
 
# Loading work.g_mac_top
 
 
 
# Loading work.g_dpath_ctrl
 
 
 
# Loading work.g_eth_parser
 
 
 
# Loading work.g_mac_core
 
 
 
# Loading work.g_rx_top
 
 
 
# Loading work.g_rx_fsm
 
 
 
# Loading work.half_dup_dble_reg
 
 
 
# Loading work.g_rx_crc32
 
 
 
# Loading work.g_deferral_rx
 
 
 
# Loading work.g_md_intf
 
 
 
# Loading work.g_tx_top
 
 
 
# Loading work.g_deferral
 
 
 
# Loading work.g_tx_fsm
 
 
 
# Loading work.g_tx_crc32
 
 
 
# Loading work.toggle_sync
 
 
 
# Loading work.g_cfg_mgmt
 
 
 
# Loading work.s2f_sync
 
 
 
# Loading work.generic_register
 
 
 
# Loading work.req_register
 
 
 
# Loading work.stat_counter
 
 
 
# Loading work.generic_intr_stat_reg
 
 
 
# Loading work.g_mii_intf
 
 
 
# Loading work.async_fifo
 
 
 
# Loading work.wb_rd_mem2mem
 
 
 
# Loading work.wb_wr_mem2mem
 
 
 
# Loading work.uart_core
 
 
 
# Loading work.uart_cfg
 
 
 
# Loading work.stat_register
 
 
 
# Loading work.uart_txfsm
 
 
 
# Loading work.uart_rxfsm
 
 
 
# Loading work.double_sync_low
 
 
 
# Loading work.spi_core
 
 
 
# Loading work.spi_if
 
 
 
# Loading work.spi_ctl
 
 
 
# Loading work.spi_cfg
 
 
 
# Loading work.oc8051_top
 
 
 
# Loading work.oc8051_decoder
 
 
 
# Loading work.oc8051_alu
 
 
 
# Loading work.oc8051_multiply
 
 
 
# Loading work.oc8051_divide
 
 
 
# Loading work.oc8051_ram_top
 
 
 
# Loading work.oc8051_ram_256x8_two_bist
 
 
 
# Loading work.oc8051_alu_src_sel
 
 
 
# Loading work.oc8051_comp
 
 
 
# Loading work.oc8051_cy_select
 
 
 
# Loading work.oc8051_indi_addr
 
 
 
# Loading work.oc8051_memory_interface
 
 
 
# Loading work.oc8051_sfr
 
 
 
# Loading work.oc8051_acc
 
 
 
# Loading work.oc8051_b_register
 
 
 
# Loading work.oc8051_sp
 
 
 
# Loading work.oc8051_dptr
 
 
 
# Loading work.oc8051_psw
 
 
 
# Loading work.oc8051_ports
 
 
 
# Loading work.oc8051_int
 
 
 
# Loading work.oc8051_tc
 
 
 
# Loading work.oc8051_tc2
 
 
 
# Loading work.oc8051_xrom
 
 
 
# Loading work.oc8051_xram
 
 
 
# Loading work.tb_eth_top
 
 
 
# Loading work.tb_mii
 
 
 
# Loading work.tb_rmii
 
 
 
# Loading work.uart_agent
 
 
 
# Loading work.m25p20
 
 
 
# Loading work.memory_access
 
 
 
# Loading work.acdc_check
 
 
 
# Loading work.internal_logic
 
 
 
# Loading work.AT45DB321
 
 
 
# Loading work.tb_glbl
 
 
 
# Loading work.bit_register
 
 
 
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(397): [TOFD] - System task or function '$shm_open' is not defined.
 
 
 
#
 
 
 
#         Region: /tb_top
 
 
 
# ** Warning: (vsim-PLI-3003) ../tb/tb_top.v(398): [TOFD] - System task or function '$shm_probe' is not defined.
 
 
 
#
 
 
 
#         Region: /tb_top
 
 
 
# ** Warning: (vsim-3017) ../tb/tb_top.v(235): [TFMPC] - Too few port connections. Expected 50, found 44.
 
 
 
#
 
 
 
#         Region: /tb_top/u_core
 
 
 
# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_txd'. The port definition is at: ../../rtl/core/digital_core.v(29).
 
 
 
#
 
 
 
#         Region: /tb_top/u_core
 
 
 
# ** Warning: (vsim-3015) ../tb/tb_top.v(235): [PCDPC] - Port size (8 or 8) does not match connection size (4) for port 'phy_rxd'. The port definition is at: ../../rtl/core/digital_core.v(35).
 
 
 
#
 
 
 
#         Region: /tb_top/u_core
 
 
 
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_mode'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'scan_enable'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_clk'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_in'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3722) ../tb/tb_top.v(235): [TFMPC] - Missing connection for port 'mdio_out_en'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(214): [TFMPC] - Too few port connections. Expected 14, found 12.
 
 
 
#
 
 
 
#         Region: /tb_top/u_core/u_uart_core/u_rxfifo
 
 
 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'afull'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(214): [TFMPC] - Missing connection for port 'aempty'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3017) ../../rtl/uart/uart_core.v(230): [TFMPC] - Too few port connections. Expected 14, found 12.
 
 
 
#
 
 
 
#         Region: /tb_top/u_core/u_uart_core/u_txfifo
 
 
 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'afull'.
 
 
 
#
 
 
 
# ** Warning: (vsim-3722) ../../rtl/uart/uart_core.v(230): [TFMPC] - Missing connection for port 'aempty'.
 
 
 
#
 
# do run.do
 
# do run.do
 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
Line 29... Line 140... 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
 
# i : 00
 
# NOTE : Load memory with Initial delivery content
 
# NOTE : Load memory with Initial delivery content
 
# NOTE : Initial Load End
 
# NOTE : Initial Load End
 
 
 
# --> Dumpping the design
 
# NOTE: COMMUNICATION (RE)STARTED
 
# NOTE: COMMUNICATION (RE)STARTED
 
############################################
 
############################################
 
#    Testing ST Flash Read/Write Access
 
#    Testing ST Flash Read/Write Access
 
############################################
 
############################################
 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000
 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 06000000
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020240
 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8000000
 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = d8000000
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 801a0201
 
#              6775000 : tb_top.spi_sector_errase : Sending Sector Errase for Address : 000000
 
#                 6775 : tb_top.spi_sector_errase : Sending Sector Errase for Address : 000000
 
# NOTE : Sector erase cycle has begun
 
# NOTE : Sector erase cycle has begun
 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
 
# Config-Write: Id: 2 Addr = 0004, Cfg. Data = 05000000
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80020200
 
# NOTE : Only a Read Status Register instruction will be valid
 
# NOTE : Only a Read Status Register instruction will be valid
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
 
# Config-Write: Id: 2 Addr = 0000, Cfg. Data = 80220240
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#
 
#
 
# =========
 
# =========
 
# Test Status: TEST PASSED
 
# Test Status: TEST PASSED
 
# =========
 
# =========
 
#
 
#
 
# ** Note: $finish    : ../lib/tb_glbl.v(70)
 
 
 
#    Time: 2968956 ns  Iteration: 0  Instance: /tb_top
 
 

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