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// synopsys translate_off
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// synopsys translate_off
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`include "oc8051_timescale.v"
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`include "oc8051_timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module oc8051_xram (clk, rst, wr, addr, data_in, data_out, ack, stb);
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module oc8051_xram (clk, rst, wr, be, addr, data_in, data_out, ack, stb);
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//
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//
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// external data ram for simulation. part of oc8051_tb
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// external data ram for simulation. part of oc8051_tb
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// it's tehnology dependent
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// it's tehnology dependent
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//
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//
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// clk (in) clock
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// clk (in) clock
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Line 73... |
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parameter DELAY=1;
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parameter DELAY=1;
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input clk, wr, stb, rst;
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input clk, wr, stb, rst;
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input [7:0] data_in;
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input [3:0] be; // byte enable
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input [31:0] data_in;
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input [15:0] addr;
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input [15:0] addr;
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output [7:0] data_out;
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output [31:0] data_out;
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output ack;
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output ack;
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reg ackw, ackr;
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reg ackw, ackr;
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reg [7:0] data_out;
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reg [31:0] data_out;
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reg [2:0] cnt;
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reg [2:0] cnt;
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//
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//
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// buffer
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// buffer
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reg [7:0] buff [65535:0]; //64kb
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reg [7:0] buff [65535:0]; //64kb
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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begin
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begin
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if (rst)
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if (rst)
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ackw <= #1 1'b0;
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ackw <= #1 1'b0;
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else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
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else if (wr && stb && ((DELAY==3'b000) || (cnt==3'b000))) begin
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buff[addr] <= #1 data_in;
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if(be[0]) buff[addr] <= #1 data_in[7:0];
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if(be[1]) buff[addr+1] <= #1 data_in[15:8];
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if(be[2]) buff[addr+2] <= #1 data_in[23:16];
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if(be[3]) buff[addr+3] <= #1 data_in[31:24];
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ackw <= #1 1'b1;
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ackw <= #1 1'b1;
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end else ackw <= #1 1'b0;
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end else ackw <= #1 1'b0;
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end
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end
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always @(posedge clk or posedge rst)
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always @(posedge clk or posedge rst)
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if (rst)
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if (rst)
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ackr <= #1 1'b0;
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ackr <= #1 1'b0;
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else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
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else if (stb && !wr && ((DELAY==3'b000) || (cnt==3'b000))) begin
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data_out <= #1 buff[addr];
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data_out <= #1 {buff[addr+3], buff[addr+2], buff[addr+1], buff [addr]};
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ackr <= #1 1'b1;
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ackr <= #1 1'b1;
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end else begin
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end else begin
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ackr <= #1 1'b0;
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ackr <= #1 1'b0;
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data_out <= #1 8'h00;
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data_out <= #1 8'h00;
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end
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end
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