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https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
[/] [turbo8051/] [trunk/] [verif/] [run/] [run_modelsim] - Diff between revs 59 and 64
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| Rev 59 |
Rev 64 |
| Line 15... |
Line 15... |
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set risc_ext_tests=(fib divmul sort gcd cast xram)
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set risc_ext_tests=(fib divmul sort gcd cast xram)
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set risc_int_tests=(fib divmul sort gcd cast xram)
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set risc_int_tests=(fib divmul sort gcd cast xram)
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echo " Compiling with VCS "
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echo " Compiling with MODELSIM "
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./compile.modelsim | tee ../log/complie.log
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./compile.modelsim | tee ../log/complie.log
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if ($status != 0) then
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if ($status != 0) then
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| Line 98... |
Line 98... |
@ all_testsx += 1;
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@ all_testsx += 1;
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else
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else
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echo "### test ${i}: ${risc_ext_test} --> PASSED"
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echo "### test ${i}: ${risc_ext_test} --> PASSED"
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@ all_testsx += 1;
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@ all_testsx += 1;
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endif
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endif
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mv ../log/run.log ../log/x_${risc_ext_test}.log
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mv ../log/run.log ../log/ext_${risc_ext_test}.log
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end
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end
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echo "###########################################"
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echo "###########################################"
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| Line 129... |
Line 129... |
@ all_testsi += 1;
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@ all_testsi += 1;
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else
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else
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echo "### test ${i}: ${risc_int_test} --> PASSED"
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echo "### test ${i}: ${risc_int_test} --> PASSED"
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@ all_testsi += 1;
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@ all_testsi += 1;
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endif
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endif
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mv ../log/run.log ../log/x_${risc_int_test}.log
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mv ../log/run.log ../log/int_${risc_int_test}.log
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end
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end
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echo "###########################################"
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echo "###########################################"
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echo ""
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echo ""
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