URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
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| Rev 30 |
Rev 52 |
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Line 8... |
set failedx = 0;
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set failedx = 0;
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set all_testsm = 0;
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set all_testsm = 0;
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set all_testsi = 0;
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set all_testsi = 0;
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set all_testsx = 0;
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set all_testsx = 0;
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set misc_tests=(gmac_test_1 uart_test_1 spi_test_1)
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set misc_tests=(gmac_test_2 gmac_test_1 uart_test_1 spi_test_1)
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#set misc_tests=( )
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#set misc_tests=( )
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set risc_ext_tests=(fib divmul sort gcd cast xram)
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set risc_ext_tests=(fib divmul sort gcd cast xram)
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set risc_int_tests=(fib divmul sort gcd cast xram)
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set risc_int_tests=(fib divmul sort gcd cast xram)
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