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https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_tasks.v] - Diff between revs 28 and 50
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| Rev 28 |
Rev 50 |
| Line 4... |
Line 4... |
reg_cs = 0;
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reg_cs = 0;
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reg_be = 4'h0;
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reg_be = 4'h0;
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end
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end
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task cpu_read;
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task cpu_read;
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input [2:0] block_id; // 1/2/3 --> mac/spi/uart
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input [2:0] block_id;
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input [15:0] address;
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input [15:0] address;
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output [31:0] read_data;
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output [31:0] read_data;
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begin
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begin
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@(posedge app_clk);
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@(posedge app_clk);
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if(block_id == 1) reg_id = `ADDR_SPACE_MAC;
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if(block_id == 1) reg_id = `ADDR_SPACE_MAC;
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if(block_id == 2) reg_id = `ADDR_SPACE_SPI;
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if(block_id == 2) reg_id = `ADDR_SPACE_SPI;
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if(block_id == 3) reg_id = `ADDR_SPACE_UART;
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if(block_id == 3) reg_id = `ADDR_SPACE_UART;
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if(block_id == 4) reg_id = `ADDR_SPACE_RAM;
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reg_cs = 1;
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reg_cs = 1;
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reg_wr = 0;
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reg_wr = 0;
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reg_be = 4'hF;
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reg_be = 4'hF;
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reg_addr = address;
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reg_addr = address;
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@(posedge reg_ack);
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@(posedge reg_ack);
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| Line 40... |
Line 41... |
reg_wr = 1;
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reg_wr = 1;
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reg_be = 4'hF;
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reg_be = 4'hF;
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reg_addr = address;
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reg_addr = address;
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reg_wdata = write_data;
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reg_wdata = write_data;
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@(posedge reg_ack);
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@(posedge reg_ack);
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reg_wr = 0;
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@(posedge app_clk);
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@(posedge app_clk);
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reg_cs = 0;
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reg_cs = 0;
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reg_wr = 0;
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end
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end
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endtask
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endtask
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