URL
https://opencores.org/ocsvn/turbo8051/turbo8051/trunk
[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Diff between revs 15 and 27
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
Rev 15 |
Rev 27 |
Line 172... |
Line 172... |
|
|
core u_core (
|
core u_core (
|
|
|
. reset_n (reset_n ),
|
. reset_n (reset_n ),
|
. fastsim_mode (1'b1 ),
|
. fastsim_mode (1'b1 ),
|
|
|
|
`ifdef INTERNAL_ROM
|
|
. mastermode (1'b1 ),
|
|
`elsif EXTERNAL_ROM
|
|
. mastermode (1'b1 ),
|
|
`else
|
|
. mastermode (1'b0 ),
|
|
`endif
|
|
|
. xtal_clk (xtal_clk ),
|
. xtal_clk (xtal_clk ),
|
. clkout (app_clk ),
|
. clkout (app_clk ),
|
. reset_out_n (reset_out_n ),
|
. reset_out_n (reset_out_n ),
|
|
|
// Reg Bus Interface Signal
|
// Reg Bus Interface Signal
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.