URL https://opencores.org/ocsvn/turbo8051/turbo8051/trunk

Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Diff between revs 27 and 28

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Rev 27	Rev 28
Line 129...	Line 129...

`// Outputs`	`// Outputs`
`wire [31:0] reg_rdata ;`	`wire [31:0] reg_rdata ;`
`wire reg_ack ;`	`wire reg_ack ;`

	`reg master_mode ;`
	`reg ea_in ; // 1--> Internal Memory`


`wire spi_sck ;`	`wire spi_sck ;`
`wire spi_so ;`	`wire spi_so ;`
`wire spi_si ;`	`wire spi_si ;`
Line 172...	Line 174...

`core u_core (`	`core u_core (`

`. reset_n (reset_n ),`	`. reset_n (reset_n ),`
`. fastsim_mode (1'b1 ),`	`. fastsim_mode (1'b1 ),`
	`. mastermode (master_mode ),`
`ifdef INTERNAL_ROM
`. mastermode (1'b1 ),`
`elsif EXTERNAL_ROM
`. mastermode (1'b1 ),`
`else
`. mastermode (1'b0 ),`
`endif

`. xtal_clk (xtal_clk ),`	`. xtal_clk (xtal_clk ),`
`. clkout (app_clk ),`	`. clkout (app_clk ),`
`. reset_out_n (reset_out_n ),`	`. reset_out_n (reset_out_n ),`

Line 245...	Line 240...
`.wb_xram_wdata (wb_xram_wdata ),`	`.wb_xram_wdata (wb_xram_wdata ),`

`.wb_xram_stb (wb_xram_stb ),`	`.wb_xram_stb (wb_xram_stb ),`
`.wb_xram_cyc (wb_xram_cyc ),`	`.wb_xram_cyc (wb_xram_cyc ),`

`ifdef INTERNAL_ROM	`.ea_in (ea_in ) // internal ROM`
`.ea_in (1'b1 ) // internal ROM`
`else
`.ea_in (1'b0 ) // external ROM`
`endif

`);`	`);`


`oc8051_xrom oc8051_xrom1`	`oc8051_xrom oc8051_xrom1`
Line 410...	Line 401...
`end`	`end`
`end`	`end`

`initial begin`	`initial begin`

	`if ( $test$plusargs("INTERNAL_ROM") ) begin`
	`ea_in = 1;`
	`master_mode = 1;`
	`end else if ( $test$plusargs("EXTERNAL_ROM") ) begin`
	`ea_in = 0;`
	`master_mode = 1;`
	`end else begin`
	`ea_in = 0;`
	`master_mode = 0;`
	`end`

`TB_GLBL.init;	`TB_GLBL.init;
`#1000 wait(reset_out_n == 1);`	`#1000 wait(reset_out_n == 1);`

`if ( $test$plusargs("gmac_test_1") )`	`if ( $test$plusargs("gmac_test_1") )`
`gmac_test1();`	`gmac_test1();`

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Subversion Repositories turbo8051

[/] [turbo8051/] [trunk/] [verif/] [tb/] [tb_top.v] - Diff between revs 27 and 28